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US-12622319-B2 - Stacked die packaging architecture with conductive vias on interposer

US12622319B2US 12622319 B2US12622319 B2US 12622319B2US-12622319-B2

Abstract

A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Inventors

  • Thomas Wagner
  • Abdallah Bacha
  • Vishnu Prasad
  • Mohan Prashanth Javare Gowda
  • Bernd Waidhas
  • Sonja Koller
  • Eduardo De Mesa
  • Jan Proschwitz
  • Lizabeth Keser

Assignees

  • INTEL CORPORATION

Dates

Publication Date
20260505
Application Date
20220303

Claims (20)

  1. 1 . A microelectronic assembly, comprising: an interposer having a first face and a second face opposite to the first face; a plurality of integrated circuit (IC) dies in a plurality of layers on the first face of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second face of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies; wherein at least one IC die of the plurality of IC dies comprises a front metallization stack and a through silicon via (TSV) coupling the front metallization stack to a redistribution layer of the redistribution layers adjacent a back side of the at least one IC die.
  2. 2 . The microelectronic assembly of claim 1 , wherein: the IC dies are coupled between adjacent layers by first interconnects having a first pitch, the interposer is coupled to the package substrate by second interconnects having a second pitch, and the first pitch is smaller than the second pitch.
  3. 3 . The microelectronic assembly of claim 2 , wherein the IC dies form separate stacks through the layers, each stack being coupled to the interposer by the first interconnects.
  4. 4 . The microelectronic assembly of claim 1 , wherein the dielectric material is a mold compound.
  5. 5 . The microelectronic assembly of claim 1 , wherein the interposer comprises one of silicon, ceramic, and glass.
  6. 6 . The microelectronic assembly of claim 1 , wherein conductive vias in a subset of the plurality of conductive vias have larger diameters than conductive vias in another subset of the plurality of conductive vias.
  7. 7 . The microelectronic assembly of claim 6 , wherein: a first subset of the conductive vias is configured to operate at a first voltage, a second subset of the conductive vias is configured to operate at a second voltage, and the first voltage is different from the second voltage.
  8. 8 . The microelectronic assembly of claim 1 , wherein the plurality of IC dies is contained within a boundary of the interposer.
  9. 9 . The microelectronic assembly of claim 1 , wherein any two conductive vias in contact with each other and extending through adjacent layers have a common center.
  10. 10 . The microelectronic assembly of claim 1 , wherein any two conductive vias in adjacent layers do not have a common center.
  11. 11 . An IC package, comprising: a package substrate; an interposer coupled to the package substrate on a first face of the interposer; and a plurality of IC dies on a second face of the interposer, the plurality being contained within a boundary of the interposer, wherein: the IC dies are arranged in more than two layers, conductive vias extend through the layers on the second face of the interposer, and redistribution layers are adjacent to the layers, a portion of the redistribution layers coupling the conductive vias to the IC dies; wherein at least one IC die of the plurality of IC dies comprises a front metallization stack and a through silicon via (TSV) coupling the front metallization stack to a redistribution layer of the redistribution layers adjacent a back side of the at least one IC die.
  12. 12 . The IC package of claim 11 , further comprising a mold compound encasing the plurality of IC dies on the second face of the interposer.
  13. 13 . The IC package of claim 12 , wherein the mold compound has different material compositions in different layers.
  14. 14 . The IC package of claim 11 , wherein: the IC dies are in a plurality of stacks, at least one stack extending through the layers, and the conductive vias are distributed laterally between the stacks.
  15. 15 . The IC package of claim 11 , wherein the interposer is another IC die.
  16. 16 . The IC package of claim 11 , wherein the interposer comprises TSVs.
  17. 17 . The IC package of claim 11 , wherein: the IC dies in adjacent layers are coupled by die-to-die (DTD) interconnects, and the interposer is coupled to the package substrate with die-to-package-substrate (DTPS) interconnects.
  18. 18 . A method of fabricating a microelectronic assembly, the method comprising: providing an interposer having a first face and an opposing second face; forming a redistribution layer comprising conductive traces on the first face; attaching IC dies to the redistribution layer; depositing a dielectric material around the IC dies to form a layer over the interposer; planarizing an exposed surface of the layer opposite to the interposer; forming conductive vias in the layer; forming another redistribution layer comprising metal traces on the exposed surface; and repeating attaching IC dies, depositing the dielectric material, planarizing the exposed surface, forming the conductive vias, and forming another redistribution layer to generate successive layers until a desired arrangement of the microelectronic assembly is completed, wherein at least one IC die of the IC dies comprises a front metallization stack and a through silicon via (TSV) coupling the front metallization stack to the redistribution layer adjacent a back side of the at least one IC die.
  19. 19 . The method of claim 18 , wherein forming the conductive vias comprises depositing conductive pillars over the redistribution layer before attaching the IC dies, wherein at least a portion of the redistribution layer is in contact with the deposited conductive pillars.
  20. 20 . The method of claim 18 , wherein forming the conductive vias comprises etching through the dielectric material and plating conductive metal therein after planarizing the surface of the layer.

Description

TECHNICAL FIELD The present disclosure relates to techniques, methods, and apparatus directed to a stacked die packaging architecture with conductive vias on interposer. BACKGROUND Electronic circuits when commonly fabricated on a wafer of semiconductor material, such as silicon, are called integrated circuits (ICs). The wafer with such ICs is typically cut into numerous individual dies. The dies may be packaged into an IC package containing one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated onto an electronic system, such as a consumer electronic system, or servers, such as mainframes. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIG. 1 is a simplified cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure. FIG. 2 is a simplified top view of a section of an example microelectronic assembly according to some embodiments of the present disclosure. FIG. 3 is a simplified perspective view of a portion of yet another example microelectronic assembly according to some embodiments of the present disclosure. FIGS. 4A-4F are simplified cross-sectional views of various stages of manufacture of an example microelectronic assembly, according to some embodiments of the present disclosure. FIGS. 5A-5C are simplified cross-sectional views of details in different embodiments of the microelectronic assembly. FIGS. 6A-6C are simplified cross-sectional views of details in different embodiments of the microelectronic assembly. FIG. 7 is a cross-sectional view of a device package that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 8 is a cross-sectional side view of a device assembly that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 9 is a block diagram of an example computing device that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION Overview For purposes of illustrating IC packages described herein, it is important to understand phenomena that may come into play during assembly and packaging of ICs. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. High computing processors (e.g., central processing units (CPUs), graphics processing units (GPU)), servers, and field-programmable gate arrays (FPGAs)) typically use multiple IC dies in a single package. In some packages, the IC dies are arranged laterally and also stacked vertically in a 2.5D or 3D type of packaging architecture. In 2.5D or 3D packaging architecture, with a base die on the bottom and other IC dies on top, the IC dies on top of the base die communicate laterally with each other using bridge dies (e.g., Intel's embedded multi-die interconnect bridge EMIB™) or in a stacked die arrangement (e.g., Intel's Foveros™) with through-substrate vias (TSVs) in the underlying die, or in a stacked package-like arrangement (e.g., Intel's omni-directional interconnects (ODI)) with through-mold vias (TMVs) in a mold material surrounding the base die inside an interposer structure. As used herein, the term “interposer” refers to any cohesive (e.g., unbroken, continuous, singular) structure that provides mechanical and electrical coupling between an IC die and a package substrate in a microelectronic assembly and that occupies at least as large an area as the IC die. Much larger than traditional TSVs, the large TMVs have lower resistance, providing more robust power delivery simultaneously with higher bandwidth and lower latency enabled through stacking. At the same time, this approach may reduce the number of TSVs required in the base die, freeing up more area for active transistors and optimizing die size. However, in an arrangement of stacked IC dies over the base die of the interposer, such TMVs are not useful for IC dies on top of the die stack unless the IC dies on top of the die stack extend beyond a boundary (e.g., periphery, border, edge, footprint, etc.) of the base die. Using a redistribution layer (RDL) to connect the TMVs in the interposer to the die stack also does not serve to alleviate the problem of power supply to the IC dies on top of the die stack. In other words, in current packaging technologies, power and ground may b