US-12622320-B2 - Semiconductor package

US12622320B2US 12622320 B2US12622320 B2US 12622320B2US-12622320-B2

Abstract

A semiconductor package is provided. The semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the package substrate; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip, the second semiconductor chip by the adhesive film. The first and second semiconductor chips have different heights, and a thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is different from a thickness of the adhesive film at a portion thereof contacting the second semiconductor chip.

Inventors

Seungmin Kim

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220502
Priority Date: 20210615

Claims (17)

1 . A semiconductor package comprising: a package substrate; a first semiconductor chip mounted on the package substrate; a plurality of second semiconductor chips mounted on the package substrate, wherein the first semiconductor chip is arranged between the plurality of second semiconductor chips; an adhesive film provided on an upper surface of the first semiconductor chip and upper surfaces of the plurality of second semiconductor chips; and a third semiconductor chip attached to the first semiconductor chip, and the plurality of second semiconductor chips by the adhesive film, wherein a sidewall of one of the plurality of second semiconductor chips is provided on a same plane as a sidewall of the third semiconductor chip, wherein a portion of the third semiconductor chip, that faces the upper surface of the first semiconductor chip, is concave, wherein a first distance from an upper surface of the package substrate to the upper surface of the first semiconductor chip is greater than a second distance from the upper surface of the package substrate to the upper surfaces of the plurality of second semiconductor chips to correspond to the concave portion of the third semiconductor chip, and wherein a first thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is less than a second thickness of the adhesive film at a portion thereof contacting the plurality of second semiconductor chips.
2 . The semiconductor package of claim 1 , wherein the first distance is greater than the second distance by about 20 μm to about 100 μm in a vertical direction.
3 . The semiconductor package of claim 1 , wherein the adhesive film contacts a sidewall of the first semiconductor chip.
4 . The semiconductor package of claim 1 , wherein the first semiconductor chip comprises a controller chip or a logic chip, wherein the plurality of second semiconductor chips comprises a dummy chip, and wherein the third semiconductor chip comprises a memory chip.
5 . The semiconductor package of claim 1 , further comprising: a first bonding wire connecting the first semiconductor chip to the package substrate; second bonding wires connecting the plurality of second semiconductor chips to the package substrate; and a third bonding wire connecting the third semiconductor chip to the package substrate, wherein the first bonding wire and the second bonding wires penetrate through the adhesive film.
6 . The semiconductor package of claim 1 , wherein a plurality of slices of each of the plurality of second semiconductor chips and the third semiconductor chip form a chip stack.
7 . The semiconductor package of claim 1 , further comprising a molding member provided on each of the first semiconductor chip, the plurality of second semiconductor chips and the third semiconductor chip, and filling all interspaces between the first semiconductor chip and the plurality of second semiconductor chips.
8 . A semiconductor package comprising: a printed circuit board; a first semiconductor chip mounted on the printed circuit board by a first ball grid array; a plurality of second semiconductor chips mounted on the printed circuit board by a second ball grid array, wherein the first semiconductor chip is arranged between the plurality of second semiconductor chips; an adhesive film provided on an upper surface of the first semiconductor chip and upper surfaces of the plurality of second semiconductor chips; and a third semiconductor chip attached to the first semiconductor chip and the plurality of second semiconductor chips by the adhesive film, wherein a sidewall of one of the plurality of second semiconductor chips is provided on a same plane as a sidewall of the third semiconductor chip, wherein a portion of the third semiconductor chip, that faces the upper surface of the first semiconductor chip, is concave, and wherein an inactive surface of the first semiconductor chip, which contacts the adhesive film, is farther from the printed circuit board than inactive surfaces of the plurality of second semiconductor chips to correspond to the concave portion of the third semiconductor chip.
9 . The semiconductor package of claim 8 , wherein a first thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is less than a second thickness of the adhesive film at a portion thereof contacting the plurality of second semiconductor chips.
10 . The semiconductor package of claim 9 , wherein the adhesive film contacts a portion of a sidewall of the first semiconductor chip.
11 . The semiconductor package of claim 8 , wherein the plurality of second semiconductor chips comprises a plurality of dummy semiconductor chips, and wherein the first semiconductor chip is arranged between the plurality of dummy semiconductor chips.
12 . The semiconductor package of claim 11 , further comprising a molding member provided on each of the first semiconductor chip, the plurality of dummy semiconductor chips and the third semiconductor chip, and filling all interspaces between the first semiconductor chip and the plurality of dummy semiconductor chips.
13 . A semiconductor package comprising: a plurality of lower semiconductor chips apart from each other on a package substrate, the plurality of lower semiconductor chips comprising a first lower semiconductor chip and a plurality of second lower semiconductor chips, wherein the first lower semiconductor chip is arranged between the plurality of second lower semiconductor chips; a molding member filling interspaces between the plurality of lower semiconductor chips; an adhesive film provided on an active surface of the plurality of lower semiconductor chips and the molding member; and an upper semiconductor chip provided on the adhesive film, wherein a portion of a lower surface of the upper semiconductor chip, that faces the plurality of lower semiconductor chips, is concave wherein a sidewall of one of the plurality of lower semiconductor chips is provided on a same plane as a sidewall of the upper semiconductor chip, wherein the first lower semiconductor chip is narrower and has a smaller plan area than one of the plurality of second lower semiconductor chips, and wherein an active surface of the first lower semiconductor chip is closer to the upper semiconductor chip than active surfaces of the plurality of second lower semiconductor chips to correspond to the concave portion of the upper semiconductor chip.
14 . The semiconductor package of claim 13 , wherein the active surface of the first lower semiconductor chip is provided on a different plane than the active surfaces of the plurality of second lower semiconductor chips.
15 . The semiconductor package of claim 13 , wherein the first lower semiconductor chip comprises an active chip, and wherein the plurality of second lower semiconductor chips comprises a dummy chip.
16 . The semiconductor package of claim 13 , further comprising a printed circuit board, wherein inactive surfaces of the plurality of lower semiconductor chips are attached to an upper surface of the printed circuit board.
17 . The semiconductor package of claim 16 , wherein the upper semiconductor chip comprises a plurality of stacked non-volatile memories, and wherein each of the plurality of stacked non-volatile memories is connected to the printed circuit board via a bonding wire.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Korean Patent Application No. 10-2021-0077421, filed on Jun. 15, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Methods, apparatuses and systems consistent with example embodiments relate to a semiconductor package, and more particularly, to a system in package in which different types of semiconductor chips are included in a semiconductor package. Demand for portable devices that are lightweight and compact has rapidly increased in the electronic product market, and accordingly, there is a need for electronic components mounted on the electronic products have to be light and miniaturized. For the electronic components to be light and miniaturized, the semiconductor packages mounted thereon are required to process a large amount of data while a volume thereof is decreased. Accordingly, there is a need for high integration and single packaging of semiconductor chips mounted on the semiconductor packages is required. SUMMARY One or more example embodiments provide a semiconductor package including semiconductor chips having different thicknesses and on lower ends thereof, to efficiently protect different types of semiconductor chips in a limited structure of the semiconductor package. Issues solved by example embodiments are not limited to the above-mentioned issues, and other issues not mentioned may be resolved by example embodiments in view of the following description. According to an aspect of an example embodiment, a semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the package substrate; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip, the second semiconductor chip by the adhesive film. A first distance from an upper surface of the package substrate to the upper surface of the first semiconductor chip is different than a second distance from the upper surface of the package substrate to the upper surface of the second semiconductor chip, and a first thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is different from a second thickness of the adhesive film at a portion thereof contacting the second semiconductor chip. According to an aspect of an example embodiment, a semiconductor package includes: a printed circuit board; a first semiconductor chip mounted on the printed circuit board by a first ball grid array; a second semiconductor chip mounted on the printed circuit board mounted on the printed circuit board by a second ball grid array; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip and the second semiconductor chip by the adhesive film. An inactive surface of the first semiconductor chip, which contacts the adhesive film, is farther from the printed circuit board than an inactive surface of the second semiconductor chip. According to an aspect of an example embodiment, a semiconductor package includes: a plurality of lower semiconductor chips apart from each other, the plurality of lower semiconductor chips including a first lower semiconductor chip and a second lower semiconductor chip; a molding member filling interspaces between the plurality of lower semiconductor chips; an adhesive film provided on an active surface of the plurality of lower semiconductor chips and the molding member; and an upper semiconductor chip provided on the adhesive film. The first lower semiconductor chip is narrower and has a smaller plan area than the second lower semiconductor chip. According to an aspect of an example embodiment, a semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a first bonding wire connecting the first semiconductor chip to the package substrate; a plurality of second semiconductor chips mounted on the package substrate around the first semiconductor chip; a plurality of second bonding wires connecting the plurality of second semiconductor chips to the package substrate; and a third semiconductor chip attached to the first semiconductor chip and the plurality of second semiconductor chips by an adhesive film. Each of the plurality of second semiconductor chips includes a plurality of stacked volatile memories, the third semiconductor chip includes a plurality of stacked non-volatile memories, a first distance from an upper surface of the package substrate to the upper surface of the first semiconductor chip is different than a second distance from the upper surface of the package substrate to the upper surface one of the p