US-12622321-B2 - Semiconductor device including through-silicon via (TSV) test device and operating method thereof

US12622321B2US 12622321 B2US12622321 B2US 12622321B2US-12622321-B2

Abstract

A semiconductor system, a semiconductor device, a through-silicon via (TSV) test method, and a method of manufacturing a semiconductor device are provided. The semiconductor system includes a semiconductor device including a buffer die and first to L-th (where L is an integer greater than or equal to 2) stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) TSVs; and a TSV test device that measures each of voltages at one end and voltages at another end on the N TSVs according to a clock signal, compares each of the voltages at the one end and the voltages at the other end with a reference voltage, and determines whether each of the N TSVs has a plurality of TSV defect types according to comparison results.

Inventors

Youngkwang Lee
Sungho Kang

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220728
Priority Date: 20210903

Claims (13)

1 . A semiconductor system comprising: a semiconductor device comprising a buffer die and first to L-th stack dies stacked on the buffer die and configured to communicate with the buffer die through N through-silicon vias (TSVs), wherein L is an integer greater than or equal to 2, and N is a positive integer; and a TSV test device comprising: a test circuit comprising a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) directly connected to one end or another end of the N TSVs, a control circuit configured to control a connection between the plurality of MOSFETs and a power supply voltage or a ground voltage, and a detector circuit comprising a plurality of comparators, wherein the control circuit is further configured to generate enable signals for testing the N TSVs, wherein the test circuit is configured to measure each of voltages at the one end and voltages at the another end of the N TSVs according to a clock signal, and wherein the detector circuit is configured to compare each of the voltages at the one end and the voltages at the another end with a reference voltage, and determine whether each of the N TSVs has a plurality of TSV defect types according to comparison results, wherein the TSV test device is further configured to test a first TSV included in the N TSVs for two or more different TSV defect types during one period of the clock signal.
2 . The semiconductor system of claim 1 , wherein the TSV test device is configured to determine the plurality of TSV defect types comprising: during any one period of the clock signal, a first TSV defect type indicating that one of both ends of a TSV of the N TSVs is fixed to the power supply voltage, a second TSV defect type indicating that one of the both ends of the TSV is fixed to the ground voltage, a third TSV defect type indicating that a path between the both ends of the TSV is open, a fourth TSV defect type indicating that the path between the both ends of the TSV is resistively open, a fifth TSV defect type indicating that the TSV is electrically connected to another TSV, and a sixth TSV defect type indicating that an insulator between the TSV and a substrate is deteriorated and thus a current flows into the substrate.
3 . The semiconductor system of claim 2 , wherein the TSV test device is further configured to measure a voltage at one end of the first TSV when the clock signal is 1, and determine that the first TSV has a fault due to the first TSV defect type or the fifth TSV defect type when the voltage at the one end of the first TSV is greater than or equal to the reference voltage.
4 . The semiconductor system of claim 3 , wherein the TSV test device is further configured to measure the voltage at the one end of the first TSV when the clock signal is 0, and determine that the first TSV has a fault due to the second TSV defect type, the third TSV defect type, or the fourth TSV defect type when the voltage of the one end of the first TSV is less than the reference voltage.
5 . The semiconductor system of claim 4 , wherein the N TSVs comprise the first TSV and a second TSV spaced apart from the first TSV by a certain distance or more, the TSV test device is further configured to measure a voltage at another end of the second TSV when the clock signal is 0, and when the voltage at the another end of the second TSV is less than the reference voltage, detect that the second TSV has a fault due to the sixth TSV defect type.
6 . The semiconductor system of claim 1 , wherein the control circuit comprises a NAND gate, N D-flip-flops, and N XOR gates, and the control circuit is further configured to control the plurality of MOSFETs using the N D-flip-flops such that the test circuit sequentially tests the N TSVs according to the clock signal.
7 . The semiconductor system of claim 6 , wherein the TSV test device comprises M test circuits connected in parallel, wherein M is greater than or equal to 2, the control circuit and the detector circuit are shared by the M test circuits, and the M test circuits test M TSVs respectively disposed in the M test circuits for two or more different TSV defect types during any one period of the clock signal.
8 . The semiconductor system of claim 1 , wherein the test circuit comprises a plurality of common MOSFETs and a plurality of common variable resistors commonly connected to the N TSVs, and the N TSVs share the clock signal based on the plurality of common MOSFETs.
9 . The semiconductor system of claim 8 , wherein, when an internal resistance value of one TSV included in the N TSVs is a target resistance value, a voltage value at the one end and a voltage value at the another end of the N TSVs are respectively set to be half of the power supply voltage by adjusting the plurality of common variable resistors, and the target resistance value is a predetermined resistance value for determining a fault.
10 . A semiconductor device comprising: at least two semiconductor chips electrically connected through at least one through-silicon via (TSV); and a TSV test device arranged on at least one of the at least two semiconductor chips, wherein the TSV test device is configured to measure at least one test voltage provided by voltage division based on a signal output through the at least one TSV, and detect whether the at least one TSV has first to third faults according to the at least one test voltage, wherein the TSV test device comprises a voltage divider comprising an upper common zone, a TSV zone, and a lower common zone, wherein the upper common zone is connected to each of a power supply voltage and an end of the at least one TSV and comprises a zeroth common resistor and a zeroth common P-channel metal oxide semiconductor (PMOS), and wherein the TSV zone comprises the at least one TSV, a first N-type metal-oxide semiconductor (NMOS), and first and second PMOSs each directly connected to the at least one TSV, the lower common zone is connected to each of a ground voltage and another end of the at least one TSV and comprises first and second common resistors, and first and second common NMOSs, and the at least one test voltage is a PIN voltage corresponding to a voltage of a node connected to the zeroth common PMOS and the first NMOS, or a TSV voltage corresponding to a voltage of a node connected to the first and second common NMOSs in parallel and the second PMOS.
11 . The semiconductor device of claim 10 , wherein the TSV test device is further configured to compare the at least one test voltage with a reference voltage, and test whether the at least one TSV has the first fault corresponding to a bridge defect or a Stuck-at-1 fault; the second fault corresponding to an open defect, a resistive-open defect, or a Stuck-at-0 fault; or the third fault corresponding to a pinhole defect, according to a comparison result.
12 . The semiconductor device of claim 11 , wherein the TSV test device is further configured to during any one period of a clock signal, test whether the at least one TSV has the first fault when the clock signal is 1, and detect the first fault when the TSV voltage is greater than or equal to the reference voltage.
13 . The semiconductor device of claim 12 , wherein the at least one TSV comprises a first TSV and a second TSV, and the TSV test device is further configured to during any one period of the clock signal, simultaneously test whether the first TSV has the second fault and test whether the second TSV has the third fault when the clock signal is 0, detect the second fault when the TSV voltage is less than the reference voltage, and detect the third fault when the PIN voltage is less than the reference voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2021-0117936, filed on Sep. 3, 2021, in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference. BACKGROUND The present disclosure relates to through-silicon via (TSV) test devices, and more particularly to semiconductor devices including a test device for detecting TSV faults and operating methods of the semiconductor devices. As the amount of data to be processed by electronic devices has recently increased, memory devices with high capacity and high bandwidth are required. To improve the degree of integration of semiconductor memories, three-dimensional (3D) arrangement technology in which a plurality of memory chips are stacked via a two-dimensional (2D) method have been applied. According to the demand trend for high-integration and high-capacity memory, structures that increase the capacity of memory by using a 3D arrangement structure of memory chips and that also increase the degree of integration of the memory by simultaneously reducing the size of the semiconductor chips are required. A TSV method, which is a packaging technology in which upper and lower ends of semiconductor chips are connected to through-silicon electrodes by drilling fine holes in the semiconductor chips, has been used as a 3D structure arrangement technology. In a 3D integrated circuit, a TSV test for determining a resistively open or short-circuit defect of a TSV may be performed by measuring a voltage passing through the TSV, and calculating a resistance value of the TSV and providing data thereon. Conventional TSV test circuits include a flip-flop and a comparator, and may detect an open and/or short-circuit defect of a TSV. However, a limited number of types of faults may be detected using conventional TSV test circuits, and the tests take a relatively long time and defect detection accuracy is low. Accordingly, there is a need for a TSV test circuit that reduces the time for testing TSVs for faults without the need of additional hardware overhead, and that may quickly and accurately detect various types of TSV faults. SUMMARY Embodiments of the inventive concepts provide a semiconductor device and system including an effective silicon-through via (TSV) test device that quickly and accurately tests a TSV without hardware overhead to detect various types of TSV defects. Embodiments of the inventive concept provide a semiconductor system including a semiconductor device including a buffer die and first to L-th stack dies stacked on the buffer die and communicating with the buffer die through N TSVs, wherein L is an integer greater than or equal to 2, and N is a positive integer; and a TSV test device that measures each of voltages at one end and voltages at another end of the N TSVs according to a clock signal, compares each of the voltages at the one end and the voltages at the another end with a reference voltage, and determines whether each of the N TSVs has a plurality of TSV defect types according to comparison results. The TSV test device further tests a first TSV included in the N TSVs for two or more different TSV defect types during one period of the clock signal. Embodiments of the inventive concepts further provide a semiconductor device including at least two semiconductor chips electrically connected through at least one TSV; and a TSV test device arranged on at least one of the at least two semiconductor chips. The TSV test device measures at least one test voltage provided by voltage division based on a signal output through the at least one TSV, and detects whether the at least one TSV has first to third faults according to the at least one test voltage. Embodiments of the inventive concepts still further provide a TSV test method including generating an enable signal for determining whether to connect at least one of a power supply voltage and a ground voltage to a first TSV; measuring a first test voltage or a second test voltage provided by voltage division based on a voltage applied to the first TSV according to the enable signal; comparing the first test voltage or the second test voltage with a reference voltage; and detecting whether the first TSV has a fault based on a comparison result. The detecting of whether the first TSV has a fault includes detecting whether the first TSV has a first fault corresponding to a bridge defect or a Stuck-at-1 fault; a second fault corresponding to an open defect, a resistive-open defect, or a Stuck-at-0 fault; or a third fault corresponding to a pinhole defect. Embodiments of the inventive concepts also provide a method of manufacturing a semiconductor device including forming the semiconductor device as including a buffer die, and first to L-th stack dies stacked on the buffer die and communicating with the buffer die through N through-silicon vias (TSVs), wherein L is an integer greater than or equal