US-12622322-B2 - Semiconductor package having ordered wire arrangement between differential pair connection pads

US12622322B2US 12622322 B2US12622322 B2US 12622322B2US-12622322-B2

Abstract

A semiconductor package includes a package substrate, first and second semiconductor chips stacked on the package substrate and wire-bonded to the package substrate. The first semiconductor chip includes first differential pair signal pads, a first option signal pad, and a first signal path control circuit. The second semiconductor chip includes second differential pair signal pads, a second option signal pad, and a second signal path control circuit. The first signal path control circuit changes a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal. The second signal path control circuit changes a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal.

Inventors

Ki Yong Lee

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20220829
Priority Date: 20220318

Claims (20)

1 . A semiconductor package comprising: a package substrate; a first semiconductor chip disposed on the package substrate and wire-bonded to the package substrate; and a second semiconductor chip stacked on the first semiconductor chip and wire-bonded to the package substrate, wherein the first semiconductor chip includes first differential pair signal pads, a first option signal pad disposed adjacent to the first differential pair signal pads, and a first signal path control circuit for controlling signal input/output of the first differential pair signal pads and the first option signal pad, wherein the second semiconductor chip includes second differential pair signal pads, a second option signal pad disposed adjacent to the second differential pair signal pads, and a second signal path control circuit for controlling signal input/output of the second differential pair signal pads and the second option signal pad, wherein the first signal path control circuit is configured to change a signal path of one of differential pair signals of the first semiconductor chip by a first control signal, and a pad to which the one of the differential pair signals reaches is changed from one of the first differential pair signal pads to the first option signal pad, along the changed signal path, wherein according to the changed signal path of the first semiconductor chip, the first option signal pad outputs the one of the differential pair signals of the first semiconductor chip into the package substrate through a first signal wire, wherein the second signal path control circuit is configured to change a signal path of one of differential pair signals of the second semiconductor chip by a second control signal, and a pad to which the one of the differential pair signals reaches is changed from one of the second differential pair signal pads to the second option signal pad, along the changed signal path, and wherein according to the changed signal path of the second semiconductor chip, the second option signal pad outputs the one of the differential pair signals of the second semiconductor chip into the package substrate through a second signal wire.
2 . The semiconductor package of claim 1 , wherein when the signal path of the one of the differential pair signals of the first semiconductor chip is changed, the one of the first differential pair signal pads is converted into a dummy pad, and wherein when the signal path of the one of the differential pair signals of the second semiconductor chip is changed, the one of the second differential pair signal pads is converted into a dummy pad.
3 . The semiconductor package of claim 1 , wherein the first signal path control circuit includes a first electrical switch that electrically connects one of first differential pair signal lines to the first option signal pad according to the first control signal, and wherein the second signal path control circuit includes a second electrical switch that electrically connects one of second differential pair signal lines to the second option signal pad according to the second control signal.
4 . The semiconductor package of claim 1 , wherein the first semiconductor chip further includes a first control signal pad that is spaced apart from the first differential pair signal pads, wherein the second semiconductor chip further includes a second control signal pad that is spaced apart from the second differential pair signal pad, wherein the first signal path control circuit receives the first control signal according to electrical activation of the first control signal pad, and wherein the second signal path control circuit receives the second control signal according to electrical activation of the second control signal pad.
5 . The semiconductor package of claim 4 , wherein the package substrate includes a power bond finger that is disposed on a substrate body of the package substrate and is wire-bonded to at least one of the first and second control signal pads, and wherein the at least one of the first and second control signal pads is electrically activated by wire-bonding with the power bond finger.
6 . The semiconductor package of claim 5 , wherein the at least one of the first and second control signal pads is electrically activated by power provided from the power bond finger.
7 . The semiconductor package of claim 4 , wherein one of the first and second control signal pads is electrically activated, and the other is electrically deactivated.
8 . The semiconductor package of claim 1 , wherein the package substrate includes first differential pair bond fingers and second differential pair bond fingers disposed adjacent to each other.
9 . The semiconductor package of claim 8 , wherein the package substrate further includes: first differential pair signal traces electrically coupled to the first differential pair bond fingers; and second differential pair signal traces electrically coupled to the second differential pair bond fingers.
10 . The semiconductor package of claim 8 , wherein the first differential pair bond fingers include a first true signal bond finger and a first complementary signal bond finger disposed adjacent to each other, wherein the second differential pair bond fingers include a second true signal bond finger and a second complementary signal bond finger disposed adjacent to each other, wherein the first differential pair signal pads include a first true signal pad and a first complementary signal pad, wherein the second differential pair signal pads include a second true signal pad and a second complementary signal pad, wherein the first true signal pad and the second true signal pad are aligned with each other in a direction, wherein the first complementary signal pad and the second complementary signal pad are aligned with each other in the direction, and wherein the first option signal pad and the second option signal pad are aligned with each other in the direction.
11 . The semiconductor package of claim 10 , wherein the signal path of the first semiconductor chip is changed, and the signal path of the second semiconductor chip is not changed, wherein the first true signal pad is bonded to the first true signal bond finger by a first true signal wire, wherein the first option signal pad is bonded to the first complementary signal bond finger by a first complementary signal wire, wherein the second true signal pad is bonded to the second true signal bonding finger by a second true signal wire, and wherein the second complementary signal pad is bonded to the second complementary signal bond finger by a second complementary signal wire.
12 . The semiconductor package of claim 11 , wherein the first complementary signal pad is a dummy pad that is electrically disconnected from the signal path of the first semiconductor chip.
13 . The semiconductor package of claim 11 , wherein one of the second true signal wire and the second complementary signal wire passes through the first complementary signal pad.
14 . A semiconductor package comprising: a package substrate; and a semiconductor chip disposed on the package substrate and wire-bonded to the package substrate, wherein the package substrate includes differential pair bond fingers disposed on a substrate body of the package substrate, wherein the semiconductor chip includes differential pair signal pads disposed on a chip body of the semiconductor chip, an option signal pad disposed adjacent to the differential pair signal pads, a control signal pad disposed on the chip body to be spaced apart from the differential pair signal pads, and a signal path control circuit, and wherein the signal path control circuit is configured to change a signal path between one of differential pair signal lines of the semiconductor chip and one of the differential pair signal pads to a signal path between the one of the differential pair signal lines of the semiconductor chip and the option signal pad, according to electrical activation of the control signal pad, and wherein according to the changed signal path of the semiconductor chip, the option signal pad outputs a signal that come from the one of the differential pair lines of the semiconductor chip into the package substrate through a signal wire.
15 . The semiconductor package of claim 14 , wherein the package substrate further includes differential pair signal traces electrically connected to the differential pair bond fingers on the substrate body.
16 . The semiconductor package of claim 14 , wherein the package substrate further includes a power bond finger disposed on the substrate body and wire-bonded to the control signal pad.
17 . The semiconductor package of claim 16 , wherein the control signal pad is electrically activated by wire-bonding of the power bond finger and the control signal pad.
18 . The semiconductor package of claim 14 , wherein the one of the differential pair signal pads is converted into a dummy pad by electrical activation of the control signal pad.
19 . The semiconductor package of claim 14 , wherein by the electrical activation of the control signal pad, the other one of the differential pair signal pads and the option signal pad are wire-bonded to the differential pair bond fingers.
20 . The semiconductor package of claim 14 , wherein the signal path control circuit includes an electrical switch that electrically connects one of the differential pair signal lines to the option signal pad according to a control signal transmitted from the control signal pad.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2022-0034159, filed on Mar. 18, 2022, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field The present disclosure generally relates to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor chip and a package substrate each having differential pair connection pads. 2. Related Art As a semiconductor chip operates at a high speed, clock signals or data signals are transmitted through a differential mode signal transmission method in order to reduce the effect of noise. The differential mode signal transmission method may refer to a signal transmission method using two signal lines as a pair. In the differential mode signal transmission method, signals having the same magnitude and opposite phases may flow on the two signal lines. Specifically, a true signal and a complementary signal may be transmitted through the two signal lines. In this case, the complementary signal may be a signal having an opposite polarity to the true signal (i.e., a signal phase shifted by 180°). When a plurality of semiconductor chips are stacked over a package substrate, there is a demand for designing signal traces of the package substrate to correspond to the differential mode signal transmission method of the semiconductor chip. Through efficient arrangement of wirings of the package substrate, the true signal and the complementary signal may be smoothly exchanged with an external system. SUMMARY A semiconductor package according to an embodiment of the present disclosure may include a package substrate, a first semiconductor chip disposed on the package substrate and wire-bonded to the package substrate, and a second semiconductor chip stacked on the first semiconductor chip and wire-bonded to the package substrate. The first semiconductor chip may include first differential pair signal pads, a first option signal pad disposed adjacent to the first differential pair signal pads, and a first signal path control circuit for controlling signal input/output of the first differential pair signal pads and the first option signal pad. The second semiconductor chip may include second differential pair signal pads, a second option signal pad disposed adjacent to the second differential pair signal pads, and a second signal path control circuit for controlling signal input/output of the second differential pair signal pads and the second option signal pad. The first signal path control circuit may change a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal, and a pad to which the one of the differential pair signals reaches is changed from one signal pad of the first differential pair signal pads to the first option signal pad, along the changed path. The second signal path control circuit may change a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal, and a pad to which one of the differential pair signals reaches is changed from one of the second differential pair signal pads to the second option signal pad along the changed path. A semiconductor package according to an embodiment of the present disclosure may include a package substrate, and a semiconductor chip disposed on the package substrate and wire-bonded to the package substrate. The package substrate may include differential pair bond fingers disposed on a substrate body of the package substrate. The semiconductor chip may include differential pair signal pads disposed on a chip body of the semiconductor chip, an option signal pad disposed adjacent to the differential pair signal pads, a control signal pad disposed on the chip body to be spaced apart from the differential pair signal pads, and a signal path control circuit. The signal path control circuit may change a signal path between one of the differential pair signal lines of the semiconductor chip and the differential pair signal pads to a signal path between the one of the differential pair signal lines of the semiconductor chip and the option signal pad, according to electrical activation of the control signal pad. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view schematically illustrating an arrangement of pads of a semiconductor chip and a package substrate according to a comparative example. FIG. 2 is a plan view schematically illustrating an arrangement of bonding wires connecting a semiconductor chip and a package substrate according to a comparative example. FIG. 3 is a plan view schematically illustrating an arrangement of bonding wires connecting a semiconductor chip and a package substrate according to another comparative example. FIG. 4 is a plan view schematically illustrating a pad configuration of a semiconductor chip and a package substrate according to an embodiment of t