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US-12622329-B2 - Interposer frame and method of manufacturing the same

US12622329B2US 12622329 B2US12622329 B2US 12622329B2US-12622329-B2

Abstract

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

Inventors

  • Jiun Yi Wu

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260505
Application Date
20230522

Claims (20)

  1. 1 . A method, comprising: receiving a dielectric substrate having a first conductive layer on a first side of the dielectric substrate and having a second conductive layer on a second side of the dielectric substrate, wherein the dielectric substrate is made of a base material and fiber glass material and the base material and the fiber glass material are continuous from the first side of the dielectric substrate to the second side of the dielectric substrate; forming a plurality of through substrate hole (TSH) openings passing through the first conductive layer, passing through the dielectric substrate, and passing through the second conductive layer; forming a seed conductive layer on sidewalls of the TSH openings; forming a main conductive layer to cover the seed conductive layer and to cover the first conductive layer and the second conductive layer; after the main conductive layer is formed, selectively removing the first conductive layer from the first side of the dielectric substrate and selectively removing the second conductive layer from the second side of the dielectric substrate while leaving the seed conductive layer and main conductive layer along the sidewalls of the TSH openings; forming a central die opening laterally surrounded by the plurality of TSH openings and whose width is greater than a width of each TSH opening of the plurality of TSH openings; arranging a first substrate comprising a first plurality of connectors proximate to the first side of the dielectric substrate; arranging a second substrate comprising a second plurality of connectors proximate to the second side of the dielectric substrate, the dielectric substrate separating the first substrate from the second substrate; forming a passivation layer on the second substrate, the passivation layer separating the second substrate from the dielectric substrate; forming a molding compound over the passivation layer, the molding compound separating the passivation layer from the dielectric substrate; and filling a TSH opening with solder to connect a connector of the first plurality of connectors to a connector of the second plurality of connectors, the solder extending continuously from the connector of the first plurality of connectors over an entire depth of the TSH opening to the connector of the second plurality of connectors.
  2. 2 . The method of claim 1 , wherein a pitch at which the plurality of TSH openings are spaced is in a range from greater than 200 μm to about 500 μm; and wherein each of the plurality of TSH openings has a width in a range from greater than 100 μm to about 200 μm.
  3. 3 . The method of claim 2 , wherein a weight percentage of the fiber glass material from the first side of the dielectric substrate to the second side of the dielectric substrate is in a range from a first value that is 5% or greater to a second value that is less than 45%.
  4. 4 . The method of claim 1 , wherein the plurality of TSH openings each pass entirely through a periphery region of the dielectric substrate and collectively surround, in a ring-like shape, a central region of the dielectric substrate in which the opening is arranged.
  5. 5 . The method of claim 1 , wherein the dielectric substrate is made of a base material and an additive and wherein the base material is selected from a group consisting of glass, silicon, gallium arsenide, epoxy, polymer, molding compound, plastic, and ceramic; and the additive is fiber glass.
  6. 6 . The method of claim 1 , wherein the main conductive layer defines a plurality of ring-like structures that collectively laterally surround a semiconductor die.
  7. 7 . The method of claim 6 , wherein the ring-like structures include copper.
  8. 8 . The method of claim 1 , wherein the dielectric substrate has a width as measured between outermost sidewalls of the dielectric substrate in a range from about 300 μm to about 300 mm.
  9. 9 . The method of claim 1 : wherein the passivation layer contacts at least a portion of a sidewall of the connector of the second plurality of connectors and also contacts a first portion of a sidewall of the solder; and wherein the molding compound covers a second portion of the sidewall of the solder.
  10. 10 . A method, comprising: receiving an interposer substrate comprising a base material and an additive, the base material selected from a group consisting of glass, silicon, gallium arsenide, epoxy, polymer, molding compound, plastic, and ceramic, and the additive comprising fiber glass; wherein a first copper layer is disposed on a first face of the interposer substrate and a second copper layer is disposed on a second face of the interposer substrate, and wherein the base material and the additive are continuous throughout the interposer substrate from the first face of the interposer substrate to the second face of the interposer substrate; forming a plurality of through substrate hole (TSH) openings passing through the first copper layer, passing through the interposer substrate, and passing through the second copper layer; forming a seed layer on sidewalls of the TSH openings; forming a main copper layer to cover the seed layer and to cover the first copper layer and the second copper layer; after the main copper layer is formed, selectively removing the first copper layer from the first face of the interposer substrate and selectively removing the second copper layer from the second face of the interposer substrate while leaving the seed layer and main copper layer along sidewalls of the TSH openings; forming a central die opening laterally surrounded by the plurality of TSH openings and whose width is greater than a width of each TSH opening of the plurality of TSH openings; arranging a first substrate comprising a first plurality of connectors proximate to the first face of the interposer substrate; arranging a second substrate comprising a second plurality of connectors proximate to the second face of the interposer substrate, the interposer substrate separating the first substrate from the second substrate; forming a passivation layer on the second substrate, the passivation layer separating the second substrate from the interposer substrate; forming a molding compound over the passivation layer, the molding compound separating the passivation layer from the interposer substrate; and filling a TSH opening with solder to connect a connector of the first plurality of connectors to a connector of the second plurality of connectors, the solder extending continuously from the connector of the first plurality of connectors over an entire depth of the TSH opening to the connector of the second plurality of connectors.
  11. 11 . The method of claim 10 , further comprising: forming a molding compound extending beneath a lower surface of the interposer substrate to vertically separate a lower surface of the interposer substrate from the second substrate, and wherein the molding compound has an upper surface that is level with or beneath an upper surface of the interposer substrate such that the molding compound does not vertically separate the upper surface of the interposer substrate from the first substrate.
  12. 12 . The method of claim 10 , wherein a pitch at which the plurality of TSH openings are spaced is in a range from about 75 μm to about 500 μm; and wherein each of the plurality of TSH openings has a width in a range from about 50 μm to about 200 μm.
  13. 13 . The method of claim 10 , wherein a weight percentage of the fiber glass from the first face to the second face of the interposer substrate is in a range from a first value that is 5% or greater to a second value that is less than 45%.
  14. 14 . The method of claim 10 , wherein the interposer substrate has a width in a range from about 300 μm to about 300 mm.
  15. 15 . The method of claim 10 : wherein the passivation layer contacts at least a portion of a sidewall of the connector of the second plurality of connectors and also contacts a first portion of a sidewall of the solder; and wherein the molding compound covers a second portion of the sidewall of the solder.
  16. 16 . A method, comprising: receiving an interposer substrate including fiberglass that has a first conductive layer on a first side of the interposer substrate and has a second conductive layer on a second side of the interposer substrate, and wherein the interposer substrate is continuous from the first side of the interposer substrate to the second side of the interposer substrate; forming a plurality of first openings passing through the first conductive layer, passing through the interposer substrate, and passing through the second conductive layer, an opening of the plurality of first openings having a first area on a lateral plane passing through the interposer substrate, the first area being defined by a first inner sidewall of the interposer substrate; forming a third conductive layer on sidewalls of the plurality of first openings; forming a fourth conductive layer to cover the third conductive layer and to cover the first conductive layer and the second conductive layer; after the fourth conductive layer is formed, selectively removing the first conductive layer from the first side of the interposer substrate and selectively removing the second conductive layer from the second side of the interposer substrate while leaving the third conductive layer and fourth conductive layer along the sidewalls of the plurality of first openings; forming a second opening laterally surrounded by the plurality of first openings, the second opening having a second area on the lateral plane passing through the interposer substrate, the second area being defined by a second inner sidewall of the interposer substrate and being greater than the first area; arranging a first substrate comprising a first plurality of connectors proximate to the first side of the interposer substrate; arranging a second substrate comprising a second plurality of connectors proximate to the second side of the interposer substrate, the interposer substrate separating the first substrate from the second substrate; and forming a passivation layer on the second substrate, the passivation layer separating the second substrate from the interposer substrate; forming a molding compound over the passivation layer, the molding compound separating the passivation layer from the interposer substrate; filling the opening with solder to connect a connector of the first plurality of connectors to a connector of the second plurality of connectors, the solder extending continuously from a height corresponding to the first side of the interposer substrate to a height corresponding to the second side of the interposer substrate.
  17. 17 . The method of claim 16 , wherein a pitch at which the plurality of first openings are spaced is in a range from about 75 μm to about 500 μm; and wherein each opening of the plurality of first openings has a width in a range from about 50 μm to about 200 μm.
  18. 18 . The method of claim 16 , wherein the plurality of first openings each pass entirely through a periphery region of the interposer substrate and collectively surround, in a ring-like shape, a central region of the interposer substrate in which the second opening is arranged.
  19. 19 . The method of claim 16 , wherein the interposer substrate has a width as measured between outermost sidewalls of the interposer substrate in a range from about 300 μm to about 300 mm.
  20. 20 . The method of claim 16 : wherein the passivation layer contacts at least a portion of a sidewall of the connector of the second plurality of connectors and also contacts a first portion of a sidewall of the solder; and wherein the molding compound covers a second portion of the sidewall of the solder.

Description

REFERENCE TO RELATED APPLICATIONS This application is a Continuation of U.S. application Ser. No. 16/953,871, filed on Nov. 20, 2020, which is a Continuation of U.S. application Ser. No. 16/578,297, filed on Sep. 21, 2019 (now U.S. Pat. No. 10,861,836, issued on Dec. 8, 2020), which is a Divisional of U.S. application Ser. No. 15/632,958, filed on Jun. 26, 2017 (now U.S. Pat. No. 10,840,224, issued on Nov. 17, 2020), which is a Continuation of U.S. application Ser. No. 13/433,210, filed on Mar. 28, 2012 (now U.S. Pat. No. 9,691,636, issued on Jun. 27, 2017), which claims the benefit of U.S. Provisional Application No. 61/594,141, filed on Feb. 2, 2012. The contents of the above-referenced patent applications are hereby incorporated by reference in their entirety. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less areas or heights than packages of the past, in some applications. Thus, new packaging technologies, such as wafer level packaging (WLP) and package on package (PoP), have begun to be developed. These relatively new types of packaging technologies for semiconductors face manufacturing challenges. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIG. 1A is a perspective view of a package using the PoP technology (also referred to as “a PoP package” or “a PoP structure”) including a package bonded to another package, which is further bonded to a substrate in accordance with some embodiments. FIG. 1B is a cross-sectional view of a portion of the PoP package of FIG. 1A cut along line P-P, in accordance with some embodiments. FIG. 2 is an exploded view of a PoP package including a package over another package, which is over yet another package in accordance with some embodiments. FIGS. 3A-3F are cross-sectional views of an interposer frame at various manufacturing stages in accordance with some embodiments. FIG. 4A is a top view of the interposer frame of FIG. 3F, in accordance with some embodiments. FIG. 4B is a top view of a portion of an interposer frame with different numbers of rows and columns, in accordance with some embodiments. FIG. 5A is a cross-sectional view of a through substrate hole (TSH) placed between two solder balls, in accordance with some embodiments. FIG. 5B is a cross-sectional view of the solder balls filling the TSH, in accordance with some embodiments. FIG. 6 is a cross-sectional view of a portion of a PoP package after the solder layers of an upper and an lower packages fill through substrate holes (TSHs) to form through substrate vias (TSVs), in accordance with some embodiments. Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative and do not limit the scope of the disclosure. FIG. 1A is a perspective view of a PoP package (or PoP structure) 100 including a package 110 bonded to another package 120, which is further bonded to a substrate 130 in accordance with some embodiments. Each package, such as package 110 or package 120, includes at least a semiconductor die (not shown). The semiconductor die includes a semiconductor substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The semiconductor substrate refers to any construction comprising semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be use