US-12622330-B2 - Stacked semiconductor package

US12622330B2US 12622330 B2US12622330 B2US 12622330B2US-12622330-B2

Abstract

A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.

Inventors

Joonghyun Baek
Jaekyu SUNG
Dongok KWAK
Taeyoung Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230613
Priority Date: 20220901

Claims (20)

1 . A stacked semiconductor package comprising: a package base substrate; a first chip stack shaped as a series of steps, the first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction; a second chip stack shaped as a series of steps, the second chip stack including a plurality of second semiconductor chips stacked sequentially on the first chip stack, each of the plurality of second semiconductor chips being shifted by the first interval in a second horizontal direction, the second horizontal direction being opposite the first horizontal direction; and a plurality of bonding wires electrically connecting the plurality of first semiconductor chips and the plurality of second semiconductor chips to the package base substrate, wherein an upper support semiconductor chip is a lowermost second semiconductor chip among the plurality of second semiconductor chips, a lower support semiconductor chip is an uppermost first semiconductor chip among the plurality of first semiconductor chips, the upper support semiconductor chip is shifted from the lower support semiconductor chip by a second interval in the second horizontal direction, the second interval is greater than the first interval.
2 . The stacked semiconductor package of claim 1 , wherein the plurality of first semiconductor chips each have a first length in the first horizontal direction, the plurality of second semiconductor chips each have the first length in the first horizontal direction, and an uppermost second semiconductor chip among the plurality of second semiconductor chips is shifted by a second length in the second horizontal direction, compared to a lowermost first semiconductor chip among the plurality of first semiconductor chips, and the second length is less than the first length.
3 . The stacked semiconductor package of claim 2 , wherein a value of the second length is equal to a value of the second interval.
4 . The stacked semiconductor package of claim 2 , wherein the second length is about 20% to about 60% of the first length.
5 . The stacked semiconductor package of claim 2 , wherein, in a top view, the upper support semiconductor chip and the lower support semiconductor chip overlap by a third length in the first horizontal direction, and the third length is about 30% to 80% of the first length.
6 . The stacked semiconductor package of claim 1 , further comprising: a controller chip adhered to the package base substrate, wherein the controller chip is apart from the first chip stack in the first horizontal direction, and the second chip stack overlaps at least a portion of the controller chip in a vertical direction.
7 . The stacked semiconductor package of claim 6 , wherein one end of all of the plurality of second semiconductor chips protrudes in the second horizontal direction relative to one end of a lowermost first semiconductor chip among the plurality of first semiconductor chips.
8 . The stacked semiconductor package of claim 1 , further comprising: a connection structure adhered to a portion of an upper surface of the lower support semiconductor chip, wherein the upper support semiconductor chip is not adhered to the portion of the upper surface of the lower support semiconductor chip, an upper surface of the connection structure includes a plurality of intermediate connection pads, and the plurality of second semiconductor chips are electrically connected to the package base substrate through the connection structure.
9 . The stacked semiconductor package of claim 8 , wherein an upper surface of the package base substrate includes a plurality of upper connection pads, upper surfaces of the plurality of first semiconductor chips and upper surfaces of the plurality of second semiconductor chips each include a plurality of chip pads; the plurality of bonding wires connect the plurality of chip pads of the plurality of first semiconductor chips to some of the plurality of upper connection pads, the plurality of chip pads of the plurality of second semiconductor chips to some of the plurality of intermediate connection pads, and other ones of the plurality of intermediate connection pads to other ones of the plurality of upper connection pads.
10 . The stacked semiconductor package of claim 8 , wherein the connection structure includes an interposer, a buffer chip, a film substrate, or a redistribution structure.
11 . The stacked semiconductor package of claim 1 , wherein the plurality of first semiconductor chips include the lower support semiconductor chip and other first semiconductor chips, the plurality of second semiconductor chips include the upper support semiconductor chip and other second semiconductor chips, a thickness of the lower support semiconductor chip is greater than thicknesses of the other first semiconductor chips, and a thickness of the upper support semiconductor chip, is thicker than thicknesses of other second semiconductor chips.
12 . A stacked semiconductor package comprising: a package base substrate; a first chip stack shaped as a series of steps, the first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction, and each of the plurality of first semiconductor chips having a first length in the first horizontal direction; a controller chip adhered to the package base substrate, the controller chip being apart from the first chip stack in the first horizontal direction; and a second chip stack shaped as a series of steps, the second chip stack including a plurality of second semiconductor chips stacked sequentially on the first chip stack, each of the plurality of second semiconductor chips being shifted by the first interval in a second horizontal direction, each of the plurality of second semiconductor chips having the first length in the first horizontal direction, the second horizontal direction being opposite the first horizontal direction, and the second chip stack overlapping at least a portion of the controller chip, wherein a lowermost second semiconductor chip, among the plurality of second semiconductor chips, is shifted by a second interval in the second horizontal direction compared to an uppermost first semiconductor chip among the plurality of first semiconductor chips, the second interval is greater than the first interval, an uppermost second semiconductor chip, among the plurality of second semiconductor chips, is shifted by a second length in the second horizontal direction compared to a lowermost first semiconductor chip among the plurality of first semiconductor chips, and the second length is less than the first length.
13 . The stacked semiconductor package of claim 12 , wherein the plurality of first semiconductor chips includes the uppermost first semiconductor chip and other first semiconductor chips, the plurality of second semiconductor chips includes the lowermost second semiconductor chip and other second semiconductor chips, the other first semiconductor chips and the other second semiconductor chips each have a first thickness, the uppermost first semiconductor chip and the lowermost second semiconductor chip each have a second thickness, and the second thickness is greater than the first thickness.
14 . The stacked semiconductor package of claim 12 , further comprising: a plurality of die adhesive films adhered to lower surfaces of the plurality of first semiconductor chips and lower surfaces of the plurality of second semiconductor chips, respectively, wherein the plurality of die adhesive films include a die adhesive film adhered to a lower surface of the lowermost first semiconductor chip, a die adhesive film adhered to a lower surface of the lowermost second semiconductor chip, and other die adhesive films, a thickness of the die adhesive film adhered to the lower surface of the lowermost first semiconductor chip and a thickness of the die adhesive film adhered to the lower surface of the lowermost second semiconductor chip are greater than thicknesses of the other die adhesive films.
15 . The stacked semiconductor package of claim 14 , further comprising: a connection structure adhered to a portion of an upper surface of the uppermost first semiconductor chip, wherein an upper surface of the package base substrate includes a plurality of upper connection pads, and upper surfaces of the plurality of first semiconductor chips and upper surfaces of the plurality of second semiconductor chips each include a plurality of chip pads; the lowermost second semiconductor chip is not adhered to the portion of the upper surface of the uppermost first semiconductor chip, an upper surface of the connection structure includes a plurality of intermediate connection pads; and a plurality of bonding wires connecting the plurality of chip pads of the plurality of first semiconductor chips to some the plurality of upper connection pads, the plurality of chip pads of the plurality of second semiconductor chips to some the plurality of intermediate connection pads, and other ones of the plurality of intermediate connection pads to other ones of the plurality of upper connection pads.
16 . The stacked semiconductor package of claim 15 , wherein portions of the plurality of bonding wires connected to the plurality of chip pads of the uppermost first semiconductor chip of the first chip stack are buried in the die adhesive film adhered to a lower surface of the lowermost second semiconductor chip.
17 . The stacked semiconductor package of claim 12 , wherein a vertical level of an upper surface of the controller chip is lower than a vertical level of an upper surface of the uppermost first semiconductor chip.
18 . A stacked semiconductor package comprising: a package base substrate; a first chip stack shaped as a series of steps, the first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction; a controller chip adhered to the package base substrate, the controller chip being apart from the first chip stack in the first horizontal direction; a second chip stack shaped as a series of steps, the second chip stack including a plurality of second semiconductor chips stacked sequentially on the first chip stack, each of the plurality of second semiconductor chips being shifted by the first interval in a second horizontal direction, the second horizontal direction being opposite the first horizontal direction, the second chip stack overlapping at least a portion of the controller chip; a connection structure adhered to a portion of an upper surface of an uppermost first semiconductor chip among the plurality of first semiconductor chips, the connection structure electrically connecting the plurality of second semiconductor chips to the package base substrate; and a plurality of bonding wires electrically connecting the plurality of first semiconductor chips and the plurality of second semiconductor chips to the package base substrate, wherein a lowermost second semiconductor chip, among the plurality of second semiconductor chips, is not adhered to the portion of the upper surface of the uppermost first semiconductor chip, the lowermost second semiconductor chip is shifted by a second interval in the second horizontal direction compared to an uppermost first semiconductor chip, among the plurality of first semiconductor chips, the second interval is greater than the first interval, the plurality of first semiconductor chips include the uppermost first semiconductor chip and other first semiconductor chips, the plurality of second semiconductor chips include the uppermost first semiconductor chip and other first semiconductor chips, the other first semiconductor chips each have a first thickness, the uppermost first semiconductor chip has a second thickness, the second thickness is greater than the first thickness, the lowermost second semiconductor chip has a third thickness, and the third thickness is greater than the first thickness and equal to or greater than the second thickness.
19 . The stacked semiconductor package of claim 18 , wherein an uppermost second semiconductor chip, among the plurality of second semiconductor chips, is shifted in the second horizontal direction by about 20% to about 60% of a length of each of the plurality of first semiconductor chips, compared to a lowermost first semiconductor chip, among the plurality of first semiconductor chips.
20 . The stacked semiconductor package of claim 18 , wherein the first thickness is about 40 μm to 80 μm, the second thickness is about 60 μm to about 100 μm, and the third thickness is about 60 μm to about 150 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0111015, filed on Sep. 1, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Inventive concepts relate to a semiconductor package, and more particularly, to a stacked semiconductor package including a plurality of stacked semiconductor chips. In accordance with the rapid development of the electronics industry and users' request, electronic devices have been increasingly reduced in size and weight. Accordingly, high integration and high capacity of semiconductor devices, which are core components of electronic devices, have been required, but there is a limit of high integration of semiconductor devices. Accordingly, a semiconductor package including a plurality of semiconductor chips has been developed in order to achieve a large capacity. In addition, as demand for semiconductor devices having large capacity has increased, a stacked semiconductor package in which a plurality of semiconductor chips included in a semiconductor package is stacked has been developed. SUMMARY Inventive concepts provide a stacked semiconductor package including a plurality of stacked semiconductor chips having structural reliability. According to an embodiment of inventive concepts, a stacked semiconductor package may include a package base substrate; a first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction to have a step shape; a second chip stack including a plurality of second semiconductor chips stacked sequentially on the first chip stack, each of the plurality of second semiconductor chips being shifted by the first interval in a second horizontal direction to have a step shape, the second direction being opposite the first horizontal direction; and a plurality of bonding wires electrically connecting the plurality of first semiconductor chips and the plurality of second semiconductor chips to the package base substrate. An upper support semiconductor chip may be a lowermost second semiconductor chip among the plurality of second semiconductor chips. A lower support semiconductor chip may be an uppermost first semiconductor chip among the plurality of first semiconductor chips. The upper support semiconductor chip may be shifted from the lower support semiconductor chip by a second interval in the second horizontal direction. The second interval may be greater than the first interval. According to an embodiment of inventive concepts, a stacked semiconductor package may include a package base substrate; a first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction to have a step shape, and each of the plurality of first semiconductor chips having a first length in the first horizontal direction; a controller chip adhered to the package base substrate, the controller chip being apart from the first chip stack in the first horizontal direction; and a second chip stack including a plurality of second semiconductor chips stacked sequentially on the first chip stack, each of the plurality of second semiconductor chips being shifted by the first interval in a second horizontal direction to have a step shape, each of the plurality of second semiconductor chips having the first length in the first horizontal direction, the second horizontal direction being opposite the first horizontal direction, and the second chip stack overlapping at least a portion of the controller chip. A lowermost second semiconductor chip, among the plurality of second semiconductor chips, may be shifted by a second interval in the second horizontal direction compared to an uppermost first semiconductor chip among the plurality of first semiconductor chips. The second interval may be greater than the first interval. An uppermost second semiconductor chip, among the plurality of second semiconductor chips, may be shifted by a second length in the second horizontal direction compared to a lowermost first semiconductor chip among the plurality of first semiconductor chips. The second length may be less than the first length. According to an embodiment of inventive concepts, a stacked semiconductor package may include a package base substrate; a first chip stack including a plurality of first semiconductor chips stacked sequentially on the package base substrate, each of the plurality of first semiconductor chips being shifted by a first interval in a first horizontal direction to have a step shape; a controller chip adhered to the package base substrate, the controller chip