US-12622332-B2 - Semiconductor package using substrate block integration

Abstract

A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.

Inventors

• Wei-Chih Chen
• Shi-Bai Chen

Assignees

• MEDIATEK INC.

Dates

Publication Date

20260505

Application Date

20230629

Claims (20)

1. 1 . A semiconductor package, comprising: a partitioned package substrate composed of a plurality of discrete substrates arranged in a side-by-side manner, wherein the plurality of discrete substrates comprises a central substrate and peripheral substrates surrounding the central substrate, wherein the plurality of discrete substrates are rearranged and adjoined together with a gap therebetween, and wherein the plurality of discrete substrates are adjoined together by using an adhesive that fills into the gap; at least one integrated circuit die mounted on a first surface of the partitioned package substrate; and a plurality of solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.
2. 2 . The semiconductor package according to claim 1 , wherein the at least one integrated circuit die is electrically connected to the partitioned package substrate through a plurality of conductive elements.
3. 3 . The semiconductor package according to claim 2 , wherein the conductive elements comprise micro-bumps, copper bumps or copper pillars.
4. 4 . The semiconductor package according to claim 1 , wherein the plurality of discrete substrates are physically separated from one another.
5. 5 . The semiconductor package according to claim 1 , wherein the gap has a width ranging between 1-3 mm.
6. 6 . The semiconductor package according to claim 1 , wherein the plurality of discrete substrates are homogeneous substrates.
7. 7 . The semiconductor package according to claim 1 , wherein the plurality of discrete substrates are heterogeneous substrates.
8. 8 . The semiconductor package according to claim 1 , wherein the plurality of discrete substrates have the same thickness.
9. 9 . The semiconductor package according to claim 1 , wherein the plurality of discrete substrates have different thicknesses.
10. 10 . The semiconductor package according to claim 1 further comprising: at least one die mounted on the first surface of the partitioned package substrate in a flip-chip manner.
11. 11 . The semiconductor package according to claim 10 , wherein the at least one die is a dummy die.
12. 12 . The semiconductor package according to claim 10 , wherein the at least one die is a memory die.
13. 13 . The semiconductor package according to claim 1 further comprising: a second integrated circuit die; and an electronic device mounted on the first surface of the partitioned package substrate.
14. 14 . The semiconductor package according to claim 13 , wherein the electronic device comprises a decoupling capacitor.
15. 15 . The semiconductor package according to claim 13 , wherein the second integrated circuit die and the electronic device do not overlap with the gap.
16. 16 . The semiconductor package according to claim 1 further comprising: an annular frame mounted on the first surface of the partitioned package substrate.
17. 17 . The semiconductor package according to claim 16 , wherein the annular frame is a metal frame.
18. 18 . The semiconductor package according to claim 16 , wherein the annular frame is attached to the first surface of the partitioned package substrate by using joint bumps.
19. 19 . The semiconductor package according to claim 16 , wherein the annular frame is attached to the first surface of the partitioned package substrate by using adhesive.
20. 20 . The semiconductor package according to claim 16 , wherein the annular frame comprise an opening for accommodating the at least one integrated circuit die.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/369,979, filed on Aug. 1, 2022. The content of the application is incorporated herein by reference. BACKGROUND The present disclosure relates generally to the field of semiconductor packaging. More particularly, the present disclosure relates to a cost-effective, large-die semiconductor package using substrate block integration (SBI). As more consumers embrace smart devices, demand grows for networking data centers, Internet of Things, smart sensors, etc. To meet these needs, semiconductor design companies are encountering challenges in chip design complexity and PPA (power, performance, area) factors in lower geometries, such as 7 nm, 5 nm, and 3 nm. Advanced packaging is playing a bigger role across the semiconductor industry. Networking equipment, servers, and smartphones are among the applications that have adopted advanced packaging. To advance a design, IC vendors develop an ASIC. Then, vendors will shrink different functions at each node and pack them onto the ASIC. But this approach is becoming more complex and expensive at each node. For example, an ASIC for switch routers or data centers may include a large die and the size of the package may typically exceed 4500 mm2, which leads to a rising cost of the ASIC package because of the low production yield of the package substrate at this size. The ASIC package with large die also encounters warpage problems. SUMMARY It is one object of the present disclosure to provide an improved large-die semiconductor package using substrate block integration (SBI) in order to solve the prior art shortcomings or deficiencies. One aspect of the invention provides a semiconductor package including a partitioned package substrate composed of discrete substrates arranged in a side-by-side manner. The discrete substrates comprise a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface. According to some embodiments, the at least one integrated circuit die is electrically connected to the partitioned package substrate through a plurality of conductive elements. According to some embodiments, the conductive elements comprise micro-bumps, copper bumps or copper pillars. According to some embodiments, the discrete substrates are physically separated from one another. According to some embodiments, the discrete substrates are rearranged and adjoined together with a gap therebetween. According to some embodiments, the discrete substrates are adjoined together by using an adhesive that fills into the gap. According to some embodiments, the gap has a width ranging between 1-3 mm. According to some embodiments, the discrete substrates are homogeneous substrates. According to some embodiments, the discrete substrates are heterogeneous substrates. According to some embodiments, the discrete substrates have the same thickness. According to some embodiments, the discrete substrates have different thicknesses. According to some embodiments, the semiconductor package further includes at least one die mounted on the first surface of the partitioned package substrate in a flip-chip manner. According to some embodiments, the at least one die is a dummy die. According to some embodiments, the at least one die is a memory die. According to some embodiments, the semiconductor package further includes a second integrated circuit die; and an electronic device mounted on the first surface of the partitioned package substrate. According to some embodiments, the electronic device comprises a decoupling capacitor. According to some embodiments, the second integrated circuit die and the electronic device do not overlap with the gap. According to some embodiments, the semiconductor package further includes an annular frame mounted on the first surface of the partitioned package substrate. According to some embodiments, the annular frame is a metal frame. According to some embodiments, the annular frame is attached to the first surface of the partitioned package substrate by using joint bumps. According to some embodiments, the annular frame is attached to the first surface of the partitioned package substrate by using adhesive. According to some embodiments, the annular frame comprise an opening for accommodating the at least one integrated circuit die. According to some embodiments, the semiconductor package further includes a mold cap encapsulating the at least one integrated circuit die and the annular frame. According to some embodiments, the semiconductor package further includes a re-distribution layer (RDL) structure on the first surface of the partitioned package substrate, wherein the at least one integrated circuit die is mo