US-12622335-B2 - Exothermic reactive bonding for semiconductor die assemblies and associated systems and methods

US12622335B2US 12622335 B2US12622335 B2US 12622335B2US-12622335-B2

Abstract

Exothermic reactive bonding for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die includes a dielectric layer having a conductive pad, where at least a portion of a surface of the dielectric layer includes a first epoxy compound. When another semiconductor die including a second epoxy compound (and another conductive pad) is brought in contact with the semiconductor die such that the first and second epoxy compounds can exothermically react, the thermal energy emanating from the exothermic reaction can facilitate bonding between the conductive pads to form interconnects between the two semiconductor dies. In some cases, the thermal energy is sufficient to form the interconnects. In other cases, the thermal energy assists the post bond annealing process to form the interconnects such that the annealing can be carried out at a lower temperature.

Inventors

Kyle K. Kirby

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20220701

Claims (8)

1 . A semiconductor die, comprising: a semiconductor substrate including integrated circuitry; a dielectric layer over the semiconductor substrate, wherein at least a portion of an upper surface of the dielectric layer opposite the semiconductor substrate includes a recessed moat filled with a first epoxy compound configured to exothermically react with a second epoxy compound, the first epoxy compound having an upper surface coplanar with the upper surface of the dielectric layer; and a conductive pad in the dielectric layer laterally surrounded by moat filled with the first epoxy compound, the conductive pad including a top surface recessed with respect to the upper surface of the dielectric layer, wherein the conductive pad is coupled with the integrated circuitry at a bottom surface of the conductive pad opposite the top surface.
2 . The semiconductor die of claim 1 , wherein the first and second epoxy compounds are configured to bond to each other in response to the first epoxy compound exothermically reacting with the second epoxy compound.
3 . The semiconductor die of claim 1 , wherein the first and second epoxy compounds are configured to cause the top surface of the conductive pad to extend toward the upper surface of the dielectric layer based on thermal expansion of the conductive pad in response to the first epoxy compound exothermically reacting with the second epoxy compound.
4 . The semiconductor die of claim 1 , wherein the first epoxy compound surrounds the conductive pad.
5 . The semiconductor die of claim 1 , wherein: the conductive pad belongs to a plurality of conductive pads in the dielectric layer; and each conductive pad of the plurality is laterally surrounded by a corresponding moat filled with the first epoxy compound.
6 . The semiconductor die of claim 1 , wherein the first and second epoxy compounds includes at least one of polyepoxides, oxirane, bisphenol-based materials, novolaks materials, aliphatic materials, halogenated materials, or glycidylamine materials.
7 . The semiconductor die of claim 1 , wherein the first epoxy compound has a thickness ranging between 10 nm to 2 μm.
8 . The semiconductor die of claim 1 , wherein the conductive pad has a width less than 1 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) The present application claims priority to U.S. Provisional Patent Application No. 63/238,330, filed Aug. 30, 2021, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to semiconductor device assemblies, and more particularly relates to exothermic reactive bonding for semiconductor die assemblies and associated systems and methods. BACKGROUND Semiconductor packages typically include one or more semiconductor dies (e.g., memory chips, microprocessor chip, imager chip) mounted on a package substrate and encased in a protective covering. The semiconductor die may include functional features, such as memory cells, processor circuits, or imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to corresponding conductive structures of the package substrate, which may be coupled to terminals outside the protective covering such that the semiconductor die can be connected to higher level circuitry. In some semiconductor packages, two or more semiconductor dies are stacked on top of each other to reduce the footprint of the semiconductor packages. The semiconductor dies in the stack may be arranged in a pattern resembling stair-steps (which may be referred to as “shingle stacking”) such that a portion of the semiconductor dies may be freely accessible—e.g., to attach bond wires to one or more bond pads located in the portion. In some cases, the semiconductor dies may be stacked in a “zig-zag” pattern to increase a space above the bond pads with respect to a semiconductor die overlying above the bond pads so as to facilitate forming the bond wires. Such arrangements, however, tend to increase overall heights of the semiconductor packages. Further, the bond wires may add to the heights and/or introduce delays in signal propagation. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the overall features and the principles of the present technology. FIG. 1 illustrates various stages of process steps for direct bonding schemes. FIGS. 2A and 2B illustrate example schematic diagrams depicting various stages of forming semiconductor die assemblies in accordance with embodiments of the present technology. FIG. 3 illustrates top-down views of conductive pads of semiconductor dies in accordance with embodiments of the present technology. FIG. 4 illustrates cross-sectional diagrams of interconnects of semiconductor die assemblies including directly bonded conductive pads in accordance with embodiments of the present technology. FIG. 5 is a block diagram schematically illustrating a system including a semiconductor die assembly in accordance with embodiments of the present technology. FIG. 6 is a flowchart of a method of forming semiconductor die assemblies in accordance with embodiments of the present technology. DETAILED DESCRIPTION Specific details of several embodiments of exothermic reactive bonding for semiconductor die assemblies, and associated systems and methods are described below. The term “semiconductor device or die” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices (or dies) include logic devices or dies, memory devices or dies, controllers, or microprocessors (e.g., central processing unit (CPU), graphics processing unit (GPU)), among others. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. Further, the term “semiconductor device or die” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished functional device. Depending upon the context in which it is used, the term “substrate” may include a semiconductor wafer, a package substrate, a semiconductor device or die, or the like. Suitable steps of the methods described herein can be performed with processing steps associated with fabricating semiconductor devices (wafer-level and/or die-level) and/or manufacturing semiconductor packages. Various computing systems or environments, e.g., high-performance computing (HPC) systems, require high bandwidth and low power consumption. Certain schemes of forming interconnects between semiconductor dies (e.g., a direct bonding scheme) may facilitate satisfying the requirements, as well as providing form-factors suitable for scaling physical dimensions (e.g., heights) of semiconductor die assemblies of the HPC systems. The direct bonding scheme includes individual conductive components (e.g., copper pads, conductive pads, bond pads) of a first semiconductor