US-12624138-B2 - Brush for cleaning wafers after chemical mechanical polishing (CMP) process

Abstract

Brushes for cleaning wafers after a Chemical Mechanical Polishing (CMP) process and methods for fabricating such brushes are provided. An exemplary method for fabricating a brush for cleaning wafers after a Chemical Mechanical Polishing (CMP) process includes forming a brush configured for contacting the wafers; and, while forming the brush, controlling formation of pores within the brush to a maximum pore dimension, wherein the maximum pore dimension is 1000 nanometers (nm).

Inventors

• JHIH-FONG LIN
• Liqing Wen
• Le Lu
• Deng-Gao Chen

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20230213

Claims (20)

1. 1 . A method for fabricating a brush, the method comprising: forming the brush; and while forming the brush, controlling formation of pores within the brush to a maximum pore dimension and a minimum pore dimension, wherein the maximum pore dimension is 1000 nanometers (nm) and wherein the minimum pore dimension is 50 nanometers (nm).
2. 2 . The method of claim 1 , wherein the brush is formed from a material, and wherein controlling formation of pores within the brush to the maximum pore dimension comprises limiting a degree of polymerization within the material to from 500 to 20,000 degrees of polymerization.
3. 3 . The method of claim 1 , wherein the brush is formed from a material, and wherein controlling formation of pores within the brush to the maximum pore dimension comprises generating nanobubbles having a maximum diameter of 1000 nanometers (nm) in the material.
4. 4 . The method of claim 1 , wherein the brush is formed from a material, and wherein controlling formation of pores within the brush to the maximum pore dimension comprises adding a pore-forming chemical as filler to the material.
5. 5 . The method of claim 1 , wherein forming the brush comprises synthesizing a polyvinyl (PVA)-copolymer material.
6. 6 . The method of claim 1 , wherein forming the brush comprises synthesizing a polyvinyl (PVA)-copolymer material with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
7. 7 . The method of claim 1 , wherein forming the brush comprises synthesizing a functionalized polyvinyl (PVA) polymer.
8. 8 . The method of claim 1 , wherein forming the brush comprises synthesizing a functionalized PVA polymer with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
9. 9 . A method for fabricating a brush for cleaning wafers after a Chemical Mechanical Polishing (CMP) process, the method comprising: forming the brush with an outer surface configured for contacting the wafers, wherein the outer surface is formed from a material selected from a PVA-copolymer material with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE) and a functionalized PVA polymer material with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
10. 10 . The method of claim 9 , wherein forming the brush comprises synthesizing the PVA-copolymer material with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
11. 11 . The method of claim 9 , wherein forming the brush comprises synthesizing the functionalized PVA polymer with a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
12. 12 . The method of claim 9 , further comprising, while forming the brush, controlling formation of pores within the brush to a maximum pore dimension.
13. 13 . The method of claim 12 , wherein controlling formation of pores within the brush to a maximum pore dimension comprises maintaining a degree of polymerization (DP) of from 500 to 20000.
14. 14 . A method for fabricating a brush, the method comprising: forming the brush from a material; and while forming the brush, generating nanobubbles having a maximum diameter of 1000 nanometers (nm) in the material.
15. 15 . The method of claim 14 , wherein the nanobubbles have a minimum nanobubble dimension of 50 nm.
16. 16 . The method of claim 14 , wherein the material is a polyvinyl (PVA)-copolymer selected from PVA-b-PS, PVA-b-PMMA, PVA-b-PEG, and PVA-b-PMA.
17. 17 . The method of claim 14 , wherein the material is a functionalized polyvinyl (PVA) polymer selected from PVA-COOH, PVA-SO 3 H, and PVA-NH 2 .
18. 18 . The method of claim 14 , wherein the material has a polymer backbone selected from cellulose, lignin, nylon, and polytetrafluoroethylene (PTFE).
19. 19 . The method of claim 14 , wherein generating nanobubbles having a maximum diameter of 1000 nanometers (nm) in the material comprises maintaining a degree of polymerization (DP) of from 500 to 20000.
20. 20 . The method of claim 14 , wherein the material is selected from a polyvinyl (PVA)-copolymer and a functionalized polyvinyl (PVA) polymer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/386,034, filed Dec. 5, 2022, which is incorporated herein by reference in its entirety. BACKGROUND Chemical Mechanical Polishing (CMP) processes are widely used in the fabrication of integrated circuits. When an integrated circuit is built up layer by layer on the surface of a semiconductor wafer, CMP processes are used to planarize the topmost layer to provide a planar surface for subsequent steps in the fabrication process. CMP processes are carried out by polishing the wafer surface against a polishing pad. A slurry containing both abrasive particles and reactive chemicals is applied to the polishing pad. The relative movement of the polishing pad and the wafer surface coupled with the reactive chemicals in the slurry allows the CMP process to planarize or polish the wafer surface by means of both physical and chemical forces. After a CMP process, the polished wafer surface is cleaned to remove CMP residue, such as organic matter and abrasive slurry particles, in order to ready the surface for subsequent photolithography processes and other steps in the fabrication process. In conventional post-CMP cleaning processes, brushes are used to remove the residue on the polished wafers. The brushes are typically formed of sponges. Although existing apparatuses and methods for a post-CMP cleaning process have been generally adequate for their intended purposes, as features sizes have reduced, conventional post-CMP cleaning processes have led to particle defect issues, such as from slurry abrasives, polish wastes, and byproducts. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic perspective view of partial elements of a post-CMP cleaning apparatus in accordance with some embodiments. FIG. 2 is a schematic side view of the post-CMP cleaning apparatus of FIG. 1 in accordance with some embodiments. FIG. 3 is a schematic perspective cutaway diagram of an exemplary brush for use in the apparatus of FIGS. 1 and 2 in accordance with some embodiments. FIG. 4 is a schematic perspective view of an exemplary brush for use in the apparatus of FIGS. 1 and 2 in accordance with some embodiments. FIGS. 5-15 are structural formulas of exemplary compounds used in forming an exemplary brush of FIG. 4 in accordance with some embodiments. FIG. 16 is a scanning electron micrograph (SEM) of a porous material forming a brush in accordance with some embodiments. FIG. 17 is a flow chart illustrating a method for fabricating a brush in accordance with some embodiments. FIG. 18 is a schematic perspective view of a CMP tool in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components. Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise orient