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US-12625109-B2 - Detection structure for chip edge cracks and detection method thereof

US12625109B2US 12625109 B2US12625109 B2US 12625109B2US-12625109-B2

Abstract

The present application discloses a detection structure for chip edge cracks and a detection method thereof. In one embodiment, the detection structure comprises a test ring located between a chip scribe line and a sealing ring, wherein the chip internally comprises two test pads for detecting continuity of the test ring, the sealing ring comprises a P-type doped ring located in a substrate and a shallow trench isolation area for isolating the sealing ring the test ring, the shallow trench isolation area is formed with N-type doped regions electrically connected to the two test pads respectively; the test ring comprises a multi-layer interconnection structure located on the substrate and the interconnection structure is electrically connected to the two test pads through the N-type doped regions. The present application can detect edge cracks caused by wafer manufacturing, die sawing, and chip packaging processes to reduce reliability risk.

Inventors

  • Xiong Zhang

Assignees

  • MONTAGE TECHNOLOGY CO., LTD.

Dates

Publication Date
20260512
Application Date
20221212
Priority Date
20211210

Claims (5)

  1. 1 . A detection structure for chip edge cracks, comprising: a test ring located between a chip scribe line and a sealing ring, wherein the chip comprises two test pads for detecting continuity of the test ring, the sealing ring comprises a P-type doped ring located in a substrate and a shallow trench isolation area for isolating the sealing ring from the test ring, the shallow trench isolation area is formed with N-type doped regions electrically connected to the two test pads respectively, the N-type doped regions are surrounded by the shallow trench isolation area to insulate the N-type doped regions from the P-type doped ring; the test ring comprises a multi-layer interconnection structure located on the substrate and the interconnection structure is electrically connected to the two test pads through the N-type doped regions.
  2. 2 . The detection structure for chip edge cracks according to claim 1 , wherein the two test pads are multiplexed internal pads of the chip, and a test switch is connected between the N-type doped region and the test pad.
  3. 3 . The detection structure for chip edge cracks according to claim 1 , wherein the test ring is located in a dummy space between the scribe line and the sealing ring.
  4. 4 . The detection structure for chip edge cracks according to claim 1 , wherein the test ring comprises 5˜8 layer interconnection structure, wherein a metal layer per 5 um length of the interconnection structure is connected by 3 vias, and a total resistance value of the multi-layer interconnection structure is 20KΩ˜30KΩ.
  5. 5 . The detection structure for chip edge cracks according to claim 1 , wherein the sealing ring comprises multi-layer interconnection structure located on the P-type doped ring.

Description

REFERENCE TO RELATED APPLICATION The present application claims priority to Chinese Application number CN2021115098089, filed on Dec. 10, 2021, the contents of which are incorporated herein by reference. TECHNICAL FIELD The present application generally relates to the field of semiconductor technology, and more specifically relates to a detection structure for chip edge cracks and a detection method thereof. BACKGROUND Wafer manufacturing, die sawing, chip packaging and other processes may cause cracks at the edge of the chip, and moisture and gas pollution at the cracks may bring reliability risk to the product. There is no real-time crack detection scheme for now, but depends on reliability test. Therefore, there is a need to provide a detection structure for chip edge cracks and a detection method thereof. SUMMARY OF THE INVENTION An object of the present application is to provide a detection structure for chip edge cracks and a detection method thereof, which can detect the edge cracks caused by the wafer manufacturing, die sawing, and chip packaging processes to reduce reliability risk. The present application discloses a detection structure for chip edge cracks, which comprises: a test ring located between a chip scribe line and a sealing ring, wherein the chip comprises two test pads for detecting continuity of the test ring, the sealing ring comprises a P-type doped ring located in a substrate and a shallow trench isolation area for isolating the sealing ring from the test ring, the shallow trench isolation area is formed with N-type doped regions electrically connected to the two test pads respectively; the test ring comprises a multi-layer interconnection structure located on the substrate and the interconnection structure is electrically connected to the two test pads through the N-type doped regions. In one embodiment, the two test pads are two dedicated continuity test pads. In one embodiment, the two test pads are multiplexed internal pads of the chip, and a test switch is connected between the N-type doped region and the test pad. In one embodiment, the test ring is located in a dummy space between the scribe line and the sealing ring. In one embodiment, the test ring comprises 5˜8 layer interconnection structure, wherein a metal layer per 5 um length of the interconnection structure is connected by 3 vias, and a total resistance value of the multi-layer interconnection structure is 20K Ω˜30K Ω. In one embodiment, the sealing ring comprises multi-layer interconnection structure located on the P-type doped ring. The present application also discloses a detection method for chip edge cracks, the detection method is applied to a detection structure for chip edge cracks which comprises: a test ring located between a chip scribe line and a sealing ring, wherein the chip comprises two test pads for detecting continuity of the test ring, the sealing ring comprises a P-type doped ring located in a substrate and a shallow trench isolation area for isolating the sealing ring from the test ring, the shallow trench isolation area is formed with N-type doped regions electrically connected to the two test pads respectively; the test ring comprises a multi-layer interconnection structure located on the substrate and the interconnection structure is electrically connected to the two test pads through the N-type doped regions; wherein the method includes the following steps: applying a first predetermined current to one of the two test pads after the chip has passed chip test, and measuring a first voltage value between the two test pads; comparing the measured first voltage value with a first threshold voltage, and determining that the chip is intact if the measured first voltage value is smaller than the first threshold voltage, and that the chip is failed if the measured first voltage value is greater than or equal to the first threshold voltage; applying a second predetermined current to one of the two test pads after the chip has passed final test, and measuring a second voltage value between the two test pads; and comparing the measured second voltage value with a second threshold voltage, and determining that the chip is intact if the measured second voltage value is smaller than the second threshold voltage, and that the chip is failed if the measured second voltage value is greater than or equal to the second threshold voltage. In one embodiment, if the two test pads are multiplexed internal pads of the chip, turning on test switches between the N-type doped regions and the test pads before applied current to the test pad, and turning off the test switches between the N-type doped regions and the test pads after measured the voltage value between the test pads. In one embodiment, the magnitude of the first predetermined current is 1 nA˜100 nA, and the magnitude of the first threshold voltage is less than 0.01 V. In one embodiment, the magnitude of the second predetermined current is 1 nA˜100 nA, and