US-12625170-B2 - Localized IR drop detection and calibration scheme to create high accuracy voltage supply across physical circuit partitions for performance gain

Abstract

Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

Inventors

• Chia How Low
• Roger Cheng

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260512

Application Date

20221024

Claims (20)

1. 1 . An apparatus, comprising: a plurality of circuit partitions; a respective leakage circuit coupled to a ground node of each circuit partition; and a circuit coupled to the ground node of each circuit partition, wherein for each circuit partition, the circuit is to detect a voltage of the ground node and, based on the detected voltage, determine a leakage setting of the respective leakage circuit which adjusts the voltage of the ground node to a uniform target voltage.
2. 2 . The apparatus of claim 1 , wherein the uniform target voltage is a positive voltage which is a predetermined fraction of a supply voltage of the plurality of circuit partitions.
3. 3 . The apparatus of claim 1 , wherein for each circuit partition, the determination of the leakage setting occurs when the circuit partition is in an idle mode.
4. 4 . The apparatus of claim 1 , wherein for each circuit partition, the determination of the leakage setting occurs before a memory reference code training.
5. 5 . The apparatus of claim 1 , wherein for each circuit partition, the determination of the leakage setting occurs during each of a read, write and idle mode of the circuit partition.
6. 6 . The apparatus of claim 1 , wherein for each circuit partition: to determine the voltage of the ground node, the circuit is to compare the voltage of the ground node to different comparison voltages, and identify one of the comparison voltages which is closest to the voltage of the ground node; and to determine the leakage setting, the circuit is to store a code, based on the one of the comparison voltages.
7. 7 . The apparatus of claim 1 , wherein the circuit comprises an operational amplifier to set a target voltage at a node, and the ground nodes of the plurality of circuit partitions are coupled to the node and at different distances from the node.
8. 8 . The apparatus of claim 1 , wherein the circuit comprises an operational amplifier to set a target voltage at a node, and the ground nodes of the plurality of circuit partitions are coupled to the node via respective paths which have different current x resistance drops.
9. 9 . The apparatus of claim 1 , wherein the circuit comprises: a finite state machine; a comparator; a multiplexer having an output coupled to an inverting input of the comparator; and a voltage source coupled to a non-inverting input of the comparator, wherein the ground node of each circuit partition is input to the multiplexer, and the finite state machine is to apply a select signal to the multiplexer to couple one of the ground nodes at a time to the inverting input of the comparator.
10. 10 . The apparatus of claim 9 , wherein for each circuit partition, to detect the voltage of the ground node: the voltage source is to apply a sequence of comparison voltages to the non-inverting input of the comparator when the ground node is coupled to the inverting input of the comparator; and the finite state machine is to evaluate an output of the comparator to select one of the comparison voltages.
11. 11 . The apparatus of claim 1 , wherein at least one of the circuit partitions comprises an unmatched receiver with decision feedback equalization.
12. 12 . The apparatus of claim 1 , wherein at least one of the circuit partitions comprises a pull up driver.
13. 13 . The apparatus of claim 1 , wherein for each circuit partition, the circuit is to periodically re-determine the leakage setting of the respective leakage circuit.
14. 14 . An apparatus, comprising: a leakage circuit coupled to a ground node of a circuit partition; and a circuit coupled to the ground node, wherein: the circuit is to detect a voltage of the ground node and, based on the detected voltage, determine a leakage setting of the leakage circuit which adjusts the voltage of the ground node to a positive voltage which is a predetermined fraction of a supply voltage of the circuit partition; the circuit is to store a code indicating the leakage setting; and the leakage circuit is responsive to the code to adjust a current leakage of the ground node.
15. 15 . The apparatus of claim 14 , wherein the circuit is to determine the leakage setting before a memory reference code training in a computing device, and to periodically re-determine the leakage setting after the memory reference code training.
16. 16 . The apparatus of claim 14 , wherein: the ground node is among multiple ground nodes; each ground node is associated with a respective circuit partition and a respective leakage circuit; the circuit is to detect voltages of a subset of the multiple ground nodes and, based on the detected voltages, determine leakage settings of the respective leakage circuits; and the circuit is to estimate a leakage setting for leakage circuits of one or more other ground nodes based on the determined leakage settings.
17. 17 . An apparatus, comprising: a finite state machine; a voltage source coupled to the finite state machine; a comparator comprising a non-inverting input coupled to the voltage source and an inverting input coupled to a multiplexer, where the multiplexer is coupled to a plurality of ground nodes of respective circuit partitions; and a feedback path between an output of the comparator and an input of the finite state machine, wherein for each ground node, the finite state machine is to determine a respective voltage of the ground node based on an output of the comparator, and to adjust the respective voltage of the ground node to a common target voltage.
18. 18 . The apparatus of claim 17 , wherein the finite state machine is to determine the respective voltage of each ground node, one ground node at a time, by selecting each ground node via the multiplexer, and evaluating the output of the comparator.
19. 19 . The apparatus of claim 17 , further comprising an operational amplifier to set a target voltage at a node, wherein the ground nodes of the respective circuit partitions are coupled to the node via respective paths which have different current x resistance drops.
20. 20 . The apparatus of claim 17 , wherein: each of the ground nodes is coupled to a respective leakage circuit; the finite state machine is coupled to each of the respective leakage circuits; and for each ground node, to provide the ground node at the common target voltage, the finite state machine is to set a leakage current of the respective leakage circuit based on the determined respective voltage.

Description

FIELD The present application generally relates to the field of computing devices and more particular to regulating the ground voltages of circuit partitions. BACKGROUND A computing system can be partitioned into a related set of functional blocks (e.g., interfaces/peripherals such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe) and Double Data Rate (DDR)), where each block includes respective circuits. An interface such as DDR PHY has partitioning into different functional blocks to allow the system to be more efficiently managed. However, because of their different locations on a DDR PHY (physical layer), various challenges are presented in supplying voltages to the different blocks (also referred to as partitions). BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIG. 1 depicts an example matched receiver 100, which is a type of circuit which may be in a memory DDR PHY data partition, in accordance with various embodiments. FIG. 2 depicts an example unmatched receiver 200, which is a type of circuit which may be in a partition, in accordance with various embodiments. FIG. 3A depicts an example transmitter/receiver 300 with a ground node at Vss=0 V, which is a type of circuit which may be in a partition, in accordance with various embodiments. FIG. 3B depicts an example transmitter/receiver 350 with a ground node at Vsshi>0 V, which is a type of circuit which may be in a partition, in accordance with various embodiments. FIG. 4 depicts an example transmitter pull up/pull down circuit 400, which is a type of circuit which may be in a partition, in accordance with various embodiments. FIG. 5 depicts a table showing changes in degradation of a circuit with and without Vsshi reliability protection, in accordance with various embodiments. FIG. 6 depicts an example circuit 600 in which a target voltage Vsshi_tgt>0 V is provided to ground nodes of a number of data partitions, but separate regulation of each ground node voltage is not provided, in accordance with various embodiments. FIG. 7 depicts an example physical (PHY) floorplan 700 of partitions of a computing device with a Vsshi generator 704 in a common partition 720, in accordance with various embodiments. FIG. 8 depicts example plots of voltage versus common/multiple data partitions, for different temperatures and different amounts of traffic, in accordance with various embodiments. FIG. 9A depicts example plots of read timing margin (left side eye) across multiple data partitions, for different temperatures, in accordance with various embodiments. FIG. 9B depicts example plots of read timing margin (right side eye) across multiple data partitions, for different temperatures, in accordance with various embodiments. FIG. 10A depicts a circuit portion 1000a for regulating ground node voltages of data partitions, in accordance with various embodiments. FIG. 10B depicts a circuit portion 1000b for regulating ground node voltages of data partitions, together with the circuit portion 1000a of FIG. 10A, in accordance with various embodiments. FIG. 11 depicts an example table of codes for adjusting the leakage current in the leakage circuits 1030, 1036, 1038 and 1040 of FIG. 10A, in accordance with various embodiments. FIG. 12 depicts plots of example signals in the circuit portions 1000a and 1000b in FIGS. 10A and 10B, respectively, in a Vsshi compensation process, in accordance with various embodiments. FIG. 13 depicts a flowchart of an example process for adjusting the leakage current in the leakage circuits 1030, 1036, 1038 and 1040 of FIG. 10A, in accordance with various embodiments. FIG. 14 illustrates an example of components that may be present in a computing system 1450 for implementing the techniques (e.g., operations, processes, methods, and methodologies) described herein. DETAILED DESCRIPTION As mentioned at the outset, various challenges are presented in supplying voltages to different partitions in a computing device such as a Double Data Rate (DDR) physical layer (PHY). For example, each partition may receive a supply voltage and a ground voltage. When the ground voltage is a positive voltage, referred to as Vsshi, the level can vary based on the position of the partition relative to a voltage source which provides the ground voltage. In particular, a current×resistance (I×R) voltage drop can vary based on the length and configuration of the path used to provide the ground voltages. This results in a location-based gradient in Vsshi. In an example implementation, the partitions include circuits for a Double Data Rate (DDR) memory. The techniques and apparatuses provided herein address the above and other issues. In