US-12625178-B2 - Automatic test equipment

US12625178B2US 12625178 B2US12625178 B2US 12625178B2US-12625178-B2

Abstract

An interface device is provided between a test head and a device under test (DUT). A socket board includes sockets each configured to mount a DUT, and a socket PCB having a first face that mounts the sockets and a second face provided with multiple back face electrodes. An interposer has a first face provided with multiple deformable electrodes and a second face provided with multiple non-deformable electrodes and is configured such that the multiple deformable electrodes are in contact with the multiple back face electrodes of the socket PCB. An FPC cable has multiple electrode pads to be coupled with the multiple non-deformable electrodes on the second face of the first interposer.

Inventors

Hiroki Ichikawa
TASUKU FUJIBE

Assignees

ADVANTEST CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230719
Priority Date: 20220722

Claims (10)

1 . An interface device provided between a test head and a device under test (DUT), comprising: a socket board comprising: a socket structured to mount the DUT; and a socket printed circuit board having a first face that mounts the socket and a second face provided with a plurality of back face electrodes; a first interposer having a first face provided with a plurality of deformable electrodes and a second face provided with a plurality of non-deformable electrodes, and structured such that the plurality of deformable electrodes are in contact with the plurality of back face electrodes of the socket printed circuit board; and wiring having a plurality of electrode pads to be coupled to the plurality of non-deformable electrodes on the second face of the first interposer.
2 . The interface device according to claim 1 , wherein the wiring is an FPC cable.
3 . The interface device according to claim 1 , comprising a frontend module comprising a plurality of pin electronics Integrated Circuits (ICs) in the form of a module, wherein the frontend module and the socket printed circuit board are coupled via the wiring.
4 . The interface device according to claim 3 , wherein the frontend module further comprises a pin electronics printed circuit board having a face structured to mount pin electronics ICs, wherein the interface device further comprises a second interposer having a first face provided with a plurality of deformable electrodes and a second face provided with a plurality of non-deformable electrodes, and structured such that the plurality of deformable electrodes are in contact with the plurality of back face electrodes of the pin electronics printed circuit board, and such that the plurality of non-deformable electrodes are coupled to a plurality of electrode pads provided to the wiring.
5 . Automatic test equipment comprising: a tester main body; a test head; and the interface device according to claim 1 , coupled to the test head.
6 . An interface device used as a wafer motherboard provided between a test head and a wafer under test, comprising: a board comprising: a probe card; and a printed circuit board having a first face that mounts the probe card and a second face provided with a plurality of back face electrodes; a first interposer having a first face provided with a plurality of deformable electrodes and a second face provided with a plurality of non-deformable electrodes, and structured such that the plurality of deformable electrodes are in contact with the plurality of back face electrodes of the printed circuit board; and wiring having a plurality of electrode pads to be coupled to the plurality of non-deformable electrodes on the second face of the first interposer.
7 . The interface device according to claim 6 , wherein the wiring is an FPC cable.
8 . The interface device according to claim 6 , comprising a frontend module comprising a plurality of pin electronics Integrated Circuits (ICs) in the form of a module, wherein the frontend module and the printed circuit board are coupled via the wiring.
9 . The interface device according to claim 8 , wherein the frontend module further comprises a pin electronics printed circuit board having a face structured to mount pin electronics ICs, wherein the interface device further comprises a second interposer having a first face provided with a plurality of deformable electrodes and a second face provided with a plurality of non-deformable electrodes, and structured such that the plurality of deformable electrodes are in contact with the plurality of back face electrodes of the pin electronics printed circuit board, and such that the plurality of non-deformable electrodes are coupled to a plurality of electrode pads provided to the wiring.
10 . Automatic test equipment comprising: a tester main body; a test head; and the interface device according to claim 6 , coupled to the test head.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present invention claims priority under 35 U.S.C. § 119 to Japanese Application, 2022-117409, filed on Jul. 22, 2022, the entire contents of which being incorporated herein by reference. BACKGROUND 1. Technical Field The present disclosure relates to an interface device of automatic test equipment. 2. Description of the Related Art Automatic test equipment (ATE) is employed to test various kinds of semiconductor devices such as memory, central processing units (CPUs), or the like. An ATE supplies a test signal to a semiconductor device to be tested (which will be referred to as a “device under test (DUT)” hereafter) and measures the response of the DUT with respect to the test signal, so as to judge the quality of the DUT, or so as to identify a defective position. FIG. 1 is a block diagram showing an ATE 10 according to a conventional technique. The ATE 10 includes a tester (which will also be referred to as a “tester main body”) 20, a test head 30, an interface device 40, and a handler 50. The tester 20 integrally controls the ATE 10. Specifically, the tester 20 executes a test program so as to control the test head 30 and the handler 50, and so as to collect measurement results. The test head 30 is provided with a hardware component that generates a test signal to be supplied to a DUT 1, and that detects a signal (which will also be referred to as a “device signal”) from the DUT. Specifically, the test head 30 is provided with a pin electronics (PE) 32, a power supply circuit (not shown), etc. The PE 32 is configured as an application specific IC (ASIC) including a driver, comparator, etc. Conventionally, the PE 32 is mounted on a printed circuit board which will also be referred to as a “PE board 34” and is housed within the test head 30. The interface device 40 will also be referred to as a High Fidelity Tester Access Fixture (HiFIX). The interface device 40 relays the electrical connection between the test head 30 and the DUT 1. The interface device 40 includes a socket board 42. The socket board 42 includes multiple sockets 44. This allows multiple DUTs 1 to be measured at the same time. In a case in which the ATE is used to provide wafer-level testing, a probe card is employed instead of the socket board 42. Multiple DUTs 1 are loaded into the multiple sockets 44 by means of the handler 50. Each DUT 1 is pressed in contact with the socket 44. After the test is completed, each DUT 1 is unloaded by means of the handler 50. As necessary, the handler 50 classifies the DUTs 1 into non-defective DUTs and defective DUTs. The interface device 40 includes a socket board 42 and multiple cables 46 that couples the socket board 42 to the test head 30. A test signal generated by the PE 32 is transmitted to each DUT 1 via the corresponding cable 46. A device signal generated by each DUT 1 is transmitted to the PE 32 via the corresponding cable 46. In recent years, dynamic random access memory (DRAM) speeds have been improving. In Graphics Double Data Rate (GDDR) memory according to the GDDR6X standard, which is mounted on graphic boards, a transmission speed of 21 Gbps has been realized using the Non Return to Zero (NRZ) method. The GDDR7 standard, which is the next generation, employs Pulse Amplitude Modulation 4 (PAM4), which provides an improved transmission speed up to 40 Gbps. The speed provided by the NRZ method is also being improved year by year, and in the next generation, the speed will be improved to on the order of 28 Gbps. In a case in which the transmission speed is higher than 20 Gbps, it is difficult for a memory tester employing a conventional architecture to provide accurate measurement. At present, there is no commercially available ATE that is capable of measuring high-speed memory having an operating speed of 28 Gbps or 40 Gbps. SUMMARY The present disclosure has been made in view of such a situation. It is an exemplary purpose of the present disclosure to provide an interface device and automatic test equipment that are capable of testing a high-speed device with high accuracy. An interface device according to an embodiment of the present disclosure is provided between a test head and a device under test (DUT). The interface device includes: a socket structured to mount the DUT; and a socket printed circuit board having a first face that mounts the socket and a second face provided with multiple back face electrodes; a first interposer having a first face provided with multiple deformable electrodes and a second face provided with multiple non-deformable electrodes, and structured such that the multiple deformable electrodes are in contact with the multiple back face electrodes of the socket printed circuit board; and wiring having multiple electrode pads to be coupled to the multiple non-deformable electrodes on the second face of the first interposer. It should be noted that any combination of the components described above, any component describ