US-12625179-B2 - Methods and apparatus to identify faults in processors

Abstract

An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.

Inventors

• Devanathan Varadarajan
• Benjamin Niewenhuis

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20240621

Claims (20)

1. 1 . A system, comprising: first circuitry configured to: obtain program instructions associated with a device under test (DUT); and cause execution of the program instructions to modify contents of a set of memory circuits of the DUT; and second circuitry configured to: determine a duration of a time window; determine a set of positions of the time window; determine a number of observable modifications of the contents of the set of memory circuits in the time window for each of the set of positions; and determine a first position out of the set of positions at which the time window provides the greatest number of observable modifications.
2. 2 . The system of claim 1 , wherein the first circuitry is configured to: cause re-execution of the program instructions; and stop the re-execution of the program instructions during the time window, wherein the time window is at the first position.
3. 3 . The system of claim 2 , further comprising: third circuitry configured to: after stopping the re-execution, store the contents of the set of memory circuits in a first set of chains; compress the first set of chains to provide a second set of chains; and mask the contents in the second set of chains corresponding to one or more unobservable modifications to provide an output.
4. 4 . The system of claim 3 , further comprising: fourth circuitry configured to: determine a multiple input signature register (MISR) value based on the output; and compare the MISR value with an expected MISR value to detect a fault in the DUT.
5. 5 . The system of claim 1 , wherein the second circuitry is configured to determine the duration of the time window based on a clock frequency of the set of memory circuits.
6. 6 . The system of claim 1 , wherein the second circuitry is configured to determine the set of positions such that the time window at one position is adjacent to the time window at a next position.
7. 7 . The system of claim 1 , wherein to determine the first position, the first circuitry is configured to: for each position of the set of positions, cause a set of re-execution of the program instructions; and for each re-execution, stop the re-execution during the time window, wherein the time window is at the position; and the second circuitry is configured to: for each re-execution, determine the number of observable modifications of the contents of the set of memory circuits in the time window; and compare the numbers of observable modifications of the set of positions with each other to determine the first position.
8. 8 . A non-transitory computer readable medium storing program instructions that, when executed by one or more processors, cause the one or more processors to: cause execution of instructions to modify contents of a set of memory circuits of a device under test (DUT); determine a set of positions of a time window; determine a number of observable modifications of the contents of the set of memory circuits in the time window for each of the set of positions; and determine a first position out of the set of positions at which the time window provides the greatest number of observable modifications.
9. 9 . The non-transitory computer readable medium of claim 8 , wherein the program instructions cause the one or more processors to: cause re-execution of the instructions; and stop the re-execution of the instructions during the time window, wherein the time window is at the first position.
10. 10 . The non-transitory computer readable medium of claim 9 , wherein the program instructions cause the one or more processors to: after stopping the re-execution, store the contents of the set of memory circuits in a first set of chains; compress the first set of chains to provide a second set of chains; and mask the contents in the second set of chains corresponding to one or more unobservable modifications to provide an output.
11. 11 . The non-transitory computer readable medium of claim 10 , wherein the program instructions cause the one or more processors to: determine a multiple input signature register (MISR) value based on the output; and compare the MISR value with an expected MISR value to detect a fault in the DUT.
12. 12 . The non-transitory computer readable medium of claim 8 , wherein the program instructions cause the one or more processors to determine a duration of the time window based on a clock frequency of the set of memory circuits.
13. 13 . The non-transitory computer readable medium of claim 12 , wherein the program instructions cause the one or more processors to slide the time window based on the duration to determine the set of positions.
14. 14 . The non-transitory computer readable medium of claim 8 , wherein to determine the first position, the program instructions cause the one or more processors to: cause a set of re-execution of the instructions; and for each re-execution, stop the re-execution during the time window, wherein the time window is at one of the set of positions; and determine the number of observable modifications of the contents of the set of memory circuits in the time window; and compare the numbers of observable modifications of the set of positions with each other to determine the first position.
15. 15 . A system, comprising: first circuitry configured to: cause performance of a first test on a device under test (DUT) to modify contents of a set of memory circuits of the DUT; cause performance of a second test on the DUT, wherein the second test is a partial portion of the first test, and wherein at least one modification of the contents of the set of memory circuits is observable during the second test but unobservable after the first test; and provide the contents of the set of memory circuits from the second test for detection of a fault in the DUT.
16. 16 . The system of claim 15 , further comprising: second circuitry configured to determine a duration and a first position of a time window, wherein the second test corresponds to the time window of the duration and at the first position.
17. 17 . The system of claim 16 , wherein the second circuitry is configured to determine the duration based on a clock frequency of the set of memory circuits.
18. 18 . The system of claim 16 , wherein to determine the first position, the first circuitry is configured to: for each position of a set of positions, cause a set of re-execution of the first test; and for each re-execution, stop the re-execution during the time window, wherein the time window is at the position; and the second circuitry is configured to: for each re-execution, determine a number of observable modifications of the contents of the set of memory circuits in the time window; and determine the first position out of the set of positions at which the time window provides the greatest number of observable modifications.
19. 19 . The system of claim 15 , further comprising: third circuitry configured to: store the contents of the set of memory circuits from the second test in a first set of chains; compress the first set of chains to provide a second set of chains; and mask the contents in the second set of chains that correspond to one or more unobservable modifications to provide an output.
20. 20 . The system of claim 19 , further comprising: fourth circuitry configured to: determine a multiple input signature register (MISR) value based on the output; and compare the MISR value with an expected MISR value to detect a fault in the DUT.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/877,607, filed Jul. 29, 2022, which claims priority to U.S. Provisional Patent Application No. 63/329,623 filed Apr. 11, 2022, titled “A Compact Technique to Improve Structural Test Coverage using Functional Checkpoint Signature Computation,” all of which are hereby incorporated herein by reference in their entireties. TECHNICAL FIELD This description relates generally to processors, and more particularly to methods and apparatus to identify faults in processors. BACKGROUND Processors are used to perform a wide variety of functions across multiple industries. In some industries, processors may be required to meet strict quality requirements. The quality requirements may be used to ensure a processor can be used in a vehicle with specific safety standards. For example, in the automotive industry, some processors may be required to have at or near 0 defective parts per million (DPPM). SUMMARY For methods and apparatus to identify faults in processors, an example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 an illustrative example of controllable, observable, and detected memory values of a device under test (DUT). FIG. 2A is an example block diagram of first computer circuitry configured to evaluate an example DUT. FIG. 2B is an example block diagram of second computer circuitry configured to evaluate an example DUT. FIG. 3 is an example block diagram of the DUT of FIG. 2A. FIG. 4 is an example block diagram of the enhanced chip access trace (ECAT) scan circuitry of FIG. 3. FIG. 5 is an illustrative example of operations executed by the ECAT scan circuitry of FIG. 4. FIG. 6 is an illustrative example of operations performed by the window determiner circuitry of FIG. 3. FIG. 7 is a flowchart representative of an example process that may be performed using machine readable instructions that can be executed and/or hardware configured to implement the computer circuitry of FIG. 2A to test the device under test (DUT) of FIG. 2A. FIG. 8 is a flowchart representative of an example process that may be performed using machine readable instructions that can be executed and/or hardware configured to implement the window determiner circuitry of FIG. 3, and/or, more the test modifier circuitry of FIG. 1 to identify an observable time window as described in FIG. 7. FIG. 9 is a state machine representative of an example process that may be performed using machine readable instructions that can be executed and/or hardware configured to implement the BITO controller circuitry of FIG. 3 to perform an ECAT scan and compute a measured a multiple input signature register (MISR) value as described in FIG. 7. The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features. DETAILED DESCRIPTION The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or like parts. Although the drawings show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended and/or irregular. Manufacturers may rely on functional Design Verification (DV) tests to determine if a processor meets the safety requirements required for use in a product. A functional DV test is a test that verifies a design conforms to its specification and performs its intended action. In many examples, Automatic Test Equipment (ATE) performs a DV test on a DUT. One manner in which an ATE may quantify the performance of a DUT is to measure the number of faults that occur during a test. In some examples, the ATE measures a stuck-at fault. A stuck-at fault refers to a signal that remains at a given logic state (i.e., a logical ‘1’ or logical ‘0’) despite instructions from a test program to switch logic states. A signal that exhibits such behavior may be referred to a