US-12625180-B2 - Diagnostic ring oscillator circuit for DC and transient characterization

Abstract

A ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device has been described. The RO circuit includes a plurality of stages coupled via an RO feedback signal line and forming an inverter chain. The plurality of stages include, for each stage, a respective CMOS inverter comprising a pair of pMOS and nMOS transistors followed by a pass gate, wherein an output of a pass gate for a stage is coupled to an input for the respective CMOS inverter of a next stage. The plurality of stages include an enable stage to enable the inverter chain to be put into a free oscillating mode or another mode in which the RO circuit does not freely oscillate. The plurality of stages include a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and pre-stage are isolated from one another.

Inventors

• Andreas KERBER
• Phillip KLIZA

Assignees

• Intel NDTM US LLC

Dates

Publication Date

20260512

Application Date

20240329

Claims (20)

1. 1 . A ring oscillator (RO) circuit, comprising: a plurality of stages coupled via an RO feedback signal line and forming an inverter chain, the plurality of stages including, for each stage, a respective Complementary Metal-Oxide Semiconductor (CMOS) inverter comprising a pair of p-channel Metal-Oxide-Semiconductor (pMOS) and N-channel Metal-Oxide-Semiconductor (nMOS) transistors followed by a pass gate, wherein an output of a pass gate for a first stage is coupled to an input for the respective CMOS inverter of a next stage; an enable stage to enable the inverter chain to be put into a free oscillating mode or a first mode in which the RO circuit does not freely oscillate; and a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and the pre-stage are coupled to respective CMOS inverters of the DUT stage and the pre-stage and isolated from one another via at least one transistor.
2. 2 . The RO circuit of claim 1 , wherein the first mode includes a mode in which: an nMOS transistor in a DUT stage CMOS inverter is isolated from a pMOS transistor in the DUT stage CMOS inverter; and, a Current-Voltage (I-V) characteristic of the nMOS transistor is measured by applying a gate bias to the nMOS transistor through the pass gate of the pre-stage and a drain bias is applied to the nMOS transistor through the pass gate of the DUT stage.
3. 3 . The RO circuit of claim 1 , wherein in the first mode, a waveform is applied to an input of a DUT stage CMOS inverter through the pass gate of the enable stage and a pre-stage CMOS inverter.
4. 4 . The RO circuit of claim 3 , wherein in the first mode, a supply rail voltage is applied to the pre-stage CMOS inverter to cause a gate of one of the nMOS and pMOS transistors in the DUT stage CMOS inverter to be overdriven.
5. 5 . The RO circuit of claim 3 , wherein in the first mode a supply rail voltage is applied to the pre-stage CMOS inverter to cause a gate of one of the nMOS and pMOS transistors in the DUT stage CMOS inverter to be underdriven.
6. 6 . The RO circuit of claim 3 , wherein in the first mode includes a supply rail voltage is applied to the DUT stage CMOS inverter cause a drain of one of the nMOS and pMOS transistors in the DUT stage inverter to be overdriven.
7. 7 . The RO circuit of claim 3 , wherein in the first mode, a supply rail voltage is applied to the DUT stage CMOS inverter to cause a drain of one of the nMOS and pMOS transistors in the DUT stage inverter to be underdriven.
8. 8 . The RO circuit of claim 1 , wherein at least one of the plurality of stages includes a trigger programmable voltage-to-time converter circuit having an input to receive a signal from the respective CMOS inverter of at least one of the plurality of stages, wherein the trigger programmable voltage-to-time converter circuit is configured to determine an amplitude of the signal.
9. 9 . An electronic device, comprising: a ring oscillator (RO) circuit comprising a plurality of stages coupled via an RO feedback signal line and forming an inverter chain, the plurality of stages including, for each stage, a respective Complementary Metal-Oxide Semiconductor (CMOS) inverter comprising a pair of p-channel Metal-Oxide-Semiconductor (pMOS) and N-channel Metal-Oxide-Semiconductor (nMOS) transistors followed by a pass gate, wherein an output of a pass gate for a first stage is coupled to an input for the respective CMOS inverter of a next stage; an enable stage to enable the inverter chain to be put into a free oscillating mode or first mode in which the RO circuit does not freely oscillate; a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and the pre-stage are coupled to respective CMOS inverters of the DUT stage and the pre-stage and isolated from one another via at least one transistor.
10. 10 . The elesctronic device of claim 9 , wherein a control transistor is coupled in series with the respective CMOS inverter of the enable stage, and is configured to receive a control signal and enable the inverter chain to operate in one of the free oscillating mode and the first mode based on the control signal.
11. 11 . The electronic device of claim 10 , wherein the first mode includes a mode in which: an nMOS transistor in a DUT stage CMOS inverter is isolated from a pMOS transistor in the DUT stage CMOS inverter; and a Current-Voltage (I-V) characteristic of the nMOS transistor is measured by applying a gate bias to the nMOS transistor through the pass gate of the pre-stage and a drain bias is applied to the nMOS transistor through the pass gate of the DUT stage.
12. 12 . The electronic device of claim 10 , wherein in the first mode, a waveform is applied to an input of a DUT stage CMOS inverter through the pass gate of the enable stage and a pre-stage CMOS inverter.
13. 13 . The electronic device of claim 12 , wherein in the first mode, a supply rail voltage is applied to the pre-stage CMOS inverter to cause a gate of one of the nMOS and pMOS transistors in the DUT stage CMOS inverter to be overdriven or underdriven.
14. 14 . The electronic device of claim 12 , wherein in the first mode, a supply rail voltage to the DUT stage CMOS inverter to cause a drain of one of the nMOS and pMOS transistors in the DUT stage inverter to be overdriven.
15. 15 . The electronic device of claim 12 , wherein in the first mode, a supply rail voltage to the DUT stage CMOS inverter to cause a drain of one of the nMOS and pMOS transistors in the DUT stage inverter to be underdriven.
16. 16 . The electronic device of claim 10 , wherein at least one of the plurality of stages includes a trigger programmable voltage-to-time converter circuit having an input to receive a signal from the respective CMOS inverter of at least one of the plurality of stages, wherein the trigger programmable voltage-to-time converter circuit is configured to determine an amplitude of the signal.
17. 17 . An apparatus, comprising: electronic measurement equipment coupled to a ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device, the RO circuit, comprising: a plurality of stages coupled via an RO feedback signal line and forming an inverter chain, the plurality of stages including: for each stage, a respective Complementary Metal-Oxide Semiconductor (CMOS) inverter comprising a pair of p-channel Metal-Oxide-Semiconductor (pMOS) and N-channel Metal-Oxide-Semiconductor (nMOS) transistors followed by a pass gate, wherein an output of a pass gate for a first stage is coupled to an input for the respective CMOS inverter of a next stage; an enable stage to enable the inverter chain to be put into a free oscillating mode or a first mode in which the RO circuit does not freely oscillate; and a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and the pre-stage are coupled to respective CMOS inverters of the DUT stage and the pre-stage and isolated from one another via at least one transistor.
18. 18 . The apparatus of claim 17 , wherein in the first mode, a waveform is applied to an input of a DUT stage CMOS inverter through the pass gate of the enable stage and a pre-stage CMOS inverter.
19. 19 . The apparatus of claim 18 , wherein in the first mode, a supply rail voltage is applied to the pre-stage CMOS inverter a gate of one of the nMOS and pMOS transistors in the DUT stage CMOS inverter to be overdriven.
20. 20 . The apparatus of claim 18 , wherein in the first mode, a supply rail voltage is applied to the DUT stage CMOS inverter to cause a drain of one of the nMOS and pMOS transistors in the DUT stage inverter to be overdriven.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of the filing date of U.S. Provisional Application No. 63/535,044, filed Aug. 28, 2023, entitled “DIAGNOSTIC RING OSCILLATOR CIRCUIT FOR DC AND TRANSIENT CHARACTERIZATION” under 35 U.S.C. § 119(e). U.S. Provisional Application No. 63/535,044 is further incorporated herein in its entirety for all purposes. BACKGROUND INFORMATION Manufacturers and designers of semiconductor devices desire to have the ability to quantify different aging phenomena and their interactions while measuring their effect on numerous parameters/metrics in situ. For example, quantifying key device degradation components like Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation remains a critical reliability challenge not only in advanced technology nodes using metal gate/high-k (MG/HK) dielectrics but also for conventional CMOS technologies with poly-Si gates and SiO2 or SiON gate dielectrics. Ring-oscillator (RO) circuits are used to capture the aging kinetics of digital circuits in CMOS technologies. The introduction of time-resolved RO characterization made it feasible to separate NBTI and CHC components during standard wafer level stress conditions (the RO circuit is integrated on a wafer having respective circuitry for multiple chips and the RO circuit is tested to measure reliability characteristics of the transistors of the multiple chips' respective circuitry). A reduction in measurement delay in RO circuit characterization was beneficial for decoupling the NBTI and CHC aging mechanisms which differ in voltage dependence and time evolution. This is consistent with what was previously observed for BTI characterization in discrete devices, which typically yielded reduced power law time evolution with shorter measurement delays. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified: FIG. 1 is a diagram showing relevant degradation mechanisms for digital circuit aging modes; FIG. 2 is a diagram showing typical applied voltage waveforms on drain and gate terminal during AC-CHC (non-zero current crossing condition) inverter and no-CHC (zero current crossing condition) inverter stress testing; FIG. 3 shows an example of a RO test configuration for testing thin oxide CMOS devices; FIG. 4 shows an example of a RO test configuration for testing thick oxide CMOS devices; FIGS. 5 and 6 illustrate example circuits for the level shifter (LS) used in the RO test configuration of FIG. 4; FIG. 7 shows a first example of a DFR RO circuit, according to one embodiment; FIGS. 7a, 7b, and 7c show further details of the DFR RO circuit of FIG. 7; FIG. 8 shows a second example of a DFR RO circuit, according to one embodiment; FIGS. 8a, 8b, and 8c show further details of the DFR RO circuit of FIG. 8; FIG. 9 is a table illustrating various parameters and input used to configure a DFR RO circuit for different types of testing; FIG. 10 shows a test configuration for performing frequency testing using a DFR RO for a CMOS device including thick oxide pMOS and nMOS transistors, according to one embodiment; FIG. 11 re-presents the circuit of FIG. 7; FIGS. 12a, 12b, 12c and 12d depict different transistor stress conditions; FIG. 13 shows an improved RO circuit; FIGS. 14a and 14b show different test mode configurations for the improved RO circuit of FIG. 13; and FIG. 15 shows a voltage-time-converter circuit and operation of the voltage-time-converter with different trigger levels relative to the input signal's amplitude. DETAILED DESCRIPTION 1.0 Introduction Embodiments of methods and apparatus for diagnostic ring oscillator (RO) circuit for DC-static and transient characterization are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore,