US-12625286-B2 - Imaging system with silicon photomultipliers and method for operating thereof

US12625286B2US 12625286 B2US12625286 B2US 12625286B2US-12625286-B2

Abstract

The present invention relates to an integrated imaging system. The integrated imaging system includes an array of analog photomultiplier elements. The integrated imaging system includes a plurality of submodules, each submodule having a number of the photomultiplier elements. The integrated imaging system includes a plurality of time-to-digital converters each associated and coupled with one of the submodules. The plurality of time-to-digital converters are configured to provide a respective timing information.

Inventors

Andrada Alexandra Muntean
Edoardo Charbon

Assignees

ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Dates

Publication Date: 20260512
Application Date: 20210727

Claims (15)

1 . An integrated imaging system comprising: an array of analog photomultiplier elements; a plurality of submodules, each submodule having a number of the photomultiplier elements; and a plurality of time-to-digital converters each associated and coupled with one of the submodules, wherein the plurality of time-to-digital converters are configured to provide a respective timing information; wherein each of the photomultiplier elements of each submodule has a photodiode, wherein a fast terminal is provided for each submodule, wherein the fast terminal is coupled, particularly via a respective capacitor, with the intermediate nodes of all of the photomultiplier elements of the respective submodule, wherein the intermediate node is provided between the respective photodiode and the respective resistor, wherein the fast terminal is connected with the corresponding time-to-digital converter.
2 . The imaging system according to claim 1 , wherein each of the photomultiplier elements of each submodule has a photodiode, particularly a single photon avalanche diode, wherein a standard terminal is provided for each submodule, wherein the standard terminal is formed by the interconnection of the anode or cathode of the photodiodes of the respective submodule, particularly via a respective resistor, wherein the standard terminal is connected with a corresponding read-out circuit to provide an energy information E associated with the number of detection events in the respective submodule during a sampling time.
3 . The imaging system according to claim 1 , wherein each of the plurality of time-to-digital converters has a ring oscillator to provide a periodic signal used for incrementing a counter during a sampling period, wherein the counter provides most significant bits of the timing information, wherein a correction unit is provided which is configured to determine a missed count of the counter and to provide a first correction bit for adding to the counter value.
4 . The imaging system according to claim 3 , wherein the correction unit is configured to generate the first correction bit depending on a state of a signal CLK_COUNT incrementing the counter and the periodic signal of the ring oscillator delayed by not more than half of the period time of the ring oscillator.
5 . The imaging system according to claim 4 , wherein phase registers are used to provide least significant bits of the timing information, wherein at least one of the phase registers is configured to latch the state of the ring oscillator according to a delayed stop signal, wherein the stop signal signalizes the end of the sampling period and wherein the delayed stop signal is delayed by not more than the half of the period time of the ring oscillator, wherein the delayed periodic signal is obtained by an output of one of the phase registers.
6 . The imaging system according to claim 1 , wherein each of the plurality of time-to-digital converters has a ring oscillator to provide a periodic signal used for incrementing a counter during a sampling period, wherein the counter provides the most significant bits of the timing information, wherein a correction unit is provided which is configured to determine an additional count of the counter and to provide a second correction bit for subtracting from the counter value.
7 . The imaging system according to claim 6 , wherein the correction unit is configured to generate the second correction bit depending on the result of verification whether the least significant bit of the counter value has changed its state briefly after end of the sampling period, wherein particularly a delay element, particularly a latch or a gate, is provided to delay the least significant bit of the counter value with respect to the end of the sampling period, wherein the result of the verification is obtained by XORing the least significant bit of the counter value and the delayed least significant bit of the counter value.
8 . The imaging system according to claim 7 , wherein the correction unit is configured to generate the second correction bit further depending on a state number of the different latch states of the ring oscillator.
9 . The positron emission tomography system including an imaging system according to claim 1 .
10 . An integrated imaging system comprising: an array of analog photomultiplier elements; a plurality of submodules, each submodule having a number of the photomultiplier elements; and a plurality of time-to-digital converters each associated and coupled with one of the submodules, wherein the plurality of time-to-digital converters are configured to provide a respective timing information; wherein each of the plurality of time-to-digital converters has a ring oscillator to provide a periodic signal used for incrementing a counter during a sampling period, wherein the counter provides most significant bits of the timing information, wherein a correction unit is provided which is configured to determine a missed count of the counter and to provide a first correction bit for adding to the counter value.
11 . The imaging system according to claim 10 , wherein the correction unit is configured to generate the first correction bit depending on a state of a signal CLK_COUNT incrementing the counter and the periodic signal of the ring oscillator delayed by not more than half of the period time of the ring oscillator.
12 . The imaging system according to claim 11 , wherein phase registers are used to provide least significant bits of the timing information, wherein at least one of the phase registers is configured to latch the state of the ring oscillator according to a delayed stop signal, wherein the stop signal signalizes the end of the sampling period and wherein the delayed stop signal is delayed by not more than the half of the period time of the ring oscillator, wherein the delayed periodic signal is obtained by an output of one of the phase registers.
13 . An integrated imaging system comprising: an array of analog photomultiplier elements; a plurality of submodules, each submodule having a number of the photomultiplier elements; and a plurality of time-to-digital converters each associated and coupled with one of the submodules, wherein the plurality of time-to-digital converters are configured to provide a respective timing information; wherein each of the plurality of time-to-digital converters has a ring oscillator to provide a periodic signal used for incrementing a counter during a sampling period, wherein the counter provides the most significant bits of the timing information, wherein a correction unit is provided which is configured to determine an additional count of the counter and to provide a second correction bit for subtracting from the counter value.
14 . The imaging system according to claim 13 , wherein the correction unit is configured to generate the second correction bit depending on the result of verification whether the least significant bit of the counter value has changed its state briefly after end of the sampling period, wherein particularly a delay element, particularly a latch or a gate, is provided to delay the least significant bit of the counter value with respect to the end of the sampling period, wherein the result of the verification is obtained by XORing the least significant bit of the counter value and the delayed least significant bit of the counter value.
15 . The imaging system according to claim 14 , wherein the correction unit is configured to generate the second correction bit further depending on a state number of the different latch states of the ring oscillator.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is the U.S. national stage application of International Application No. PCT/EP2021/071002, filed on Jul. 27, 2021, which international application was published on Feb. 2, 2023, as International Publication WO 2023/006186 A1 in the English language. The international application is incorporated herein by reference, in its entirety. TECHNICAL FIELD The present invention relates to imaging devices with an array of silicon photomultipliers with an improved timing resolution. TECHNICAL BACKGROUND During the last decades, there has been a significant interest in the development of silicon photomultipliers (SiPM) as a replacement of the well know photomultiplier tubes (PMTs) which have been widely used in medical applications, such as positron emission tomography (PET) due to their stability, low noise, suitable spectral range and fast response. Over the past 20 years, more interest has been shown towards the combination of PET and magnetic resonance imaging (MRI) scanners for clinical imaging. PET-MRI scanners are beneficial in many medical disciplines such as oncology, cardiology, pediatrics, neurology etc. as they provide both functional and anatomical information, with high spatial resolution and very good soft-tissue contrast while performing simultaneous acquisitions. Silicon photomultiplier (SiPM) arrays are arrays of avalanche photodiodes that operate above the breakdown voltage, proved to be suitable candidates for PET and PET-MRI scanners due to their robustness, insensitivity to magnetic fields, low noise, high PDE and low voltage operation. The insensitivity to magnetic fields is very important because a lot of research is put into integrating PET-MRI scanners together, as they provide both functional and anatomical information, with high spatial resolution and very good soft-tissue contrast. Basically, there are two main types of SiPMs, digital SiPMs and analog SiPMs. Digital SiPMs have the output signal directly processed on-chip, with photons being detected and converted into digital signals. Due to the additional electronics presented in the digital SiPMs, in general, the area fill factor could be highly degraded. In analog SiPMs, the output currents of each avalanche photodiode are summed up into one node and, in general, the output pulse is processed using off-chip circuits such as shaping circuits, TDCs etc. The large capacitance at the output path significantly impacts the timing performance of the detector. Furthermore, analog SiPMs usually have a lower system compactness, particularly when analog SiPMs are coupled with readout electronics which are externally provided by separate application-specific integrated circuits. The two separate entities, SiPM and readout circuitry, coupled together results in a bulkier system. Considering for example an array of analog SiPMs, each of them with its own external readout, this will result in high complexity particularly with respect to wiring. Moreover, the power dissipation of such multi-ASIC systems is very high. Main limitations of analog SiPMs can be overcome by integrating an SiPM array with on-chip electronics such as a discriminator and a time to digital converter (TDC) while keeping the sensor backward-compatible. Such an integration of analog SiPMs is e.g. disclosed in A. Muntean et al., “Blumino: the first fully integrated analog SiPM with on-chip time conversion” IEEE, DOI 10.1109/TRPMS.2020.3045081, and allows to improve the performance of a system based on analog SiPMs. Due to the improved dynamic behavior in integrated analog SiPMs there has been disclosed to provide an analog SiPM device by adding a third fast terminal in addition to the standard terminals. The fast terminal presents a lower output capacitance compared to standard terminal that makes it suitable for ultra-fast timing measurements. By having the high-speed and optimized electronics on the same silicon, the capacitive load should be substantially improved, thus improving the overall timing performance. However, the high clocking rate of the time to digital converter which evaluates the fast terminal signal, may lead to counter errors due to glitches of concurrently occurring edges of relevant signals which cannot be corrected after the timing data has been read out. Document US 2011/147,567 A1 discloses a silicon photomultiplier comprising multiple photodetection cells clusters connected in parallel. Each cluster has its own read-out circuit which includes an analog-to-digital converter which converts the energy information received by each cluster into a digital signal. Moreover, the read-out circuit generates timing triggers using, for example, a CFD or leading edge tracker. It is an object of the present invention to provide an imaging system with segmented silicon photomultipliers with an improved timing resolution. SUMMARY OF THE INVENTION This object is achieved by the imaging system having silicon photomultip