US-12625319-B2 - Waveguide transitions for hybrid thin-silicon/III-V photonics

Abstract

A device comprises a substrate having lower and upper silicon layers separated by a lower dielectric layer and a III-V structure bonded to the substrate, with first, second, and third sections along an optical axis. The first section comprises a first upper waveguide segment of the upper silicon layer, increasing in width from a first width to a second width at an interface between the first and second sections, the III-V structure overlapping with a tapered portion of the first upper waveguide segment. The second section comprises a second upper waveguide segment of the upper silicon layer decreasing in width, and a first lower waveguide segment of the lower silicon layer wider than the second upper waveguide segment at the interface between the second and third sections. The third section comprises a second lower waveguide segment of the lower silicon layer.

Inventors

• Han Yun
• Erik Johan Norberg
• John Parker

Assignees

• OPENLIGHT PHOTONICS, INC.

Dates

Publication Date

20260512

Application Date

20231030

Claims (20)

1. 1 . A device comprising: a substrate comprising lower and upper silicon layers separated by a lower dielectric layer; a III-V structure bonded to the substrate; and formed in the substrate and the III-V structure, a waveguide transition structure comprising first, second, and third sections along an optical axis, wherein: the first section comprises a first upper waveguide segment formed in the upper silicon layer, the first upper waveguide segment increasing in width from a first width to a second width at an interface between the first and second sections, the III-V structure overlapping with the first upper waveguide segment; the second section comprises a second upper waveguide segment formed in the upper silicon layer and a first lower waveguide segment formed in the lower silicon layer, the second upper waveguide segment decreasing in width from the second width at the interface between the first and second sections to a third width at an interface between the second and third sections, the first lower waveguide segment decreasing in width from a fifth width at the interface between the first and second sections to a fourth width at the interface between the second and third sections, the fifth width being greater than the second width, the fourth width being greater than the third width; and the third section comprises a second lower waveguide segment having the fourth width, formed in the lower silicon layer contiguously with the first lower waveguide segment.
2. 2 . The device of claim 1 , wherein the first section further comprises a slab in the lower silicon layer.
3. 3 . The device of claim 1 , wherein the first section further comprises a third lower waveguide segment that increases in width from the first width to the second width at the interface between the first and second sections, and wherein the first lower waveguide segment has the fourth width.
4. 4 . The device of claim 1 , further comprising a top dielectric layer separating the III-V structure from the upper silicon layer.
5. 5 . The device of claim 4 , wherein the top dielectric layer has a thickness less than 100 nm.
6. 6 . The device of claim 1 , wherein the lower silicon layer and upper silicon layer each have a thickness between 100 nm and 300 nm.
7. 7 . The device of claim 1 , wherein the III-V structure includes a curved portion angled away from the optical axis, the curved portion decoupling the III-V structure from the upper silicon layer in at least a portion of the second section.
8. 8 . The device of claim 7 , wherein the curved portion of the III-V structure terminates in a light trapping structure.
9. 9 . The device of claim 6 , wherein the lower silicon layer comprises an optical modulator comprising a doped p-n junction.
10. 10 . The device of claim 1 , further comprising: germanium formed on at least one of the lower silicon layer or the upper silicon layer; and one or more photodetectors comprising the germanium and the at least one of the lower silicon layer or the upper silicon layer.
11. 11 . The device of claim 1 , wherein the first width of the first upper waveguide segment is 0.3 μm or less, and the second width of the first upper waveguide segment is between 1 μm and 3 μm.
12. 12 . The device of claim 1 , wherein the third width of the second upper waveguide segment is 0.5 μm or less.
13. 13 . The device of claim 1 , wherein the fourth width of the second lower waveguide segment is between 0.5 μm and 3 μm.
14. 14 . The device of claim 1 , wherein the third section is free of the upper silicon layer and the III-V structure.
15. 15 . The device of claim 1 , wherein the III-V structure comprises a mesa-type p-i-n structure.
16. 16 . The device of claim 15 , wherein the mesa-type p-i-n structure comprises: a bottom layer of n-type III-V material; a slab of optically active III-V material disposed above the bottom layer; and a rib of p-type III-V material disposed above the slab, the rib of p-type III-V material being narrower than the slab of optically active III-V material.
17. 17 . A method of manufacturing a photonic device, the method comprising: providing a substrate comprising a lower silicon layer disposed on an insulating layer, the substrate comprising a first section, second section, and third section arranged sequentially along an optical axis of the photonic device; forming an upper silicon layer over the lower silicon layer in the first and second sections with a lower dielectric layer separating the upper and lower silicon layers; patterning the upper silicon layer to form: a first upper waveguide segment in the first section, the first upper waveguide segment increasing in width from a first width to a second width at an interface between the first and second sections; and a second upper waveguide segment in the second section, the second upper waveguide segment decreasing in width from the second width at the interface between the first and second sections to a third width at an interface between the second and third sections; patterning the lower silicon layer to form: a first lower waveguide segment in the second section decreasing in width from a fifth width at the interface between the first and second sections to a fourth width at the interface between the second and third sections, the fifth width being greater than the second width, the fourth width being greater than the third width; and a second lower waveguide segment in the third section having the fourth width, formed in the lower silicon layer contiguously with the first lower waveguide segment; forming a top dielectric layer above the upper silicon layer; bonding a III-V semiconductor structure to the top dielectric layer in the first section; and patterning the III-V semiconductor structure to form a III-V waveguide overlapping the first upper waveguide segment in the first section.
18. 18 . The method of claim 17 , further comprising patterning the lower silicon layer to form a slab in the lower silicon layer in the first section.
19. 19 . The method of claim 17 , further comprising patterning the lower silicon layer to form a third lower waveguide segment in the first section that increases in width from the first width to the second width at the interface between the first and second sections; wherein the first lower waveguide segment has the fourth width.
20. 20 . The method of claim 17 , further comprising: forming germanium on at least one of the lower silicon layer or the upper silicon layer; and forming one or more photodetectors comprising the germanium.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from U.S. Provisional Patent Application Ser. No. 63/421,644, filed Nov. 2, 2022, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to optical devices and more particularly to optical waveguides. BACKGROUND Silicon photonics enables low-cost integrated optical circuits. Hybrid silicon/III-V material platforms, moreover, facilitate integrating lasers, among other active devices, into the optical circuits directly on-chip, eliminating the need for light to be coupled into the optical circuits from external light sources, as would result in optical coupling losses and degrade power efficiency. Hybrid silicon/III-V optical circuits generally include waveguide transition structures to couple light between silicon waveguides and III-V waveguides. In wafers with silicon device layer thicknesses of around 500 nm, efficient waveguide transitions can be formed from silicon width tapers along which the mode effective refractive index can vary between values higher and lower than the refractive index of the III-V waveguide. Many foundries, however, use wafers with silicon device layer thicknesses of about 220 nm, which allow for higher-speed silicon optical modulators. Such thin silicon layers result in a refractive index mismatch between the silicon and III-V waveguides that cannot be overcome with conventional silicon tapers. Accordingly, to leverage the benefits of both hybrid silicon/III-V and thin-silicon photonic circuits, new waveguide transition structures are needed. BRIEF DESCRIPTION OF THE DRAWINGS Described herein, with reference to the accompanying drawings, are waveguide transitions for thin-silicon/III-V platforms. FIGS. 1A and 1B are cross-sectional and top views, respectively, of an example staged waveguide transition structure with a double-layered silicon transition waveguide, in accordance with one embodiment. FIGS. 1C-1E are illustrations of the optical mode in cross sections of the staged waveguide transition structure of FIGS. 1A and 1B at various locations along the double-layered silicon transition waveguide. FIGS. 2A-2C show a sequence of cross sections illustrating an example method of manufacturing the staged waveguide transition structure of FIGS. 1A-1E. FIG. 3 is a top view of a staged waveguide transition structure, illustrating a III-V waveguide diverging from an optical axis of the silicon transition waveguide, in accordance with one embodiment. FIGS. 4A and 4B are cross-sectional and top views, respectively, of a staged waveguide transition structure with a double-layered silicon transition waveguide, in accordance with another embodiment. DESCRIPTION As described above, conventional manufacturing techniques may result in an optical refractive index mismatch between silicon waveguides and III-V waveguides that cannot be corrected by adjusting the width of the silicon waveguide. The light mode's effective index in a thin silicon waveguide of 220 nm in thickness is much smaller than in the III-V waveguide. It is challenging to lower the effective index in III-V waveguide to match that in the silicon waveguide, and low loss transitions typically cannot be achieved using only silicon tapers. Described herein are waveguide transition structures that achieve the optical coupling between a III-V compound semiconductor waveguide and a silicon waveguide of a thin-silicon photonic circuit in two stages. In the first stage, light is coupled between the III-V waveguide and a double-layered silicon transition waveguide that includes a lower silicon waveguide formed in a thin lower silicon layer, where the thin-silicon photonic circuit is implemented, and an upper silicon waveguide formed in an upper silicon layer of generally comparable thickness that is separated from the lower silicon layer by a thin dielectric layer. In the second stage, light is coupled from the upper silicon waveguide of the double-layered structure into the lower silicon waveguide. In a region underneath the III-V waveguide, the upper and/or lower silicon waveguide are generally tapered to increase in width (or “taper up”) in a direction of light propagation to efficiently couple the light from the III-V waveguide into the double-layered silicon transition waveguide. In a subsequent region in which the optical mode is carried fully in the silicon transition waveguide, the upper silicon waveguide is generally tapered to decrease in width (or “taper down) in the direction of light propagation, down to a width smaller than that of the silicon waveguide of the photonic circuit, to efficiently couple the light out of the upper silicon waveguide and into the lower silicon waveguide. Beneficially, the double-layered transition waveguide achieves the requisite effective index match for transferring light from III-V to silicon by providing an overall higher thickness locally underneath the III-V wav