US-12625406-B2 - Active matrix substrate and liquid crystal display device

US12625406B2US 12625406 B2US12625406 B2US 12625406B2US-12625406-B2

Abstract

An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

Inventors

Atsushi HACHIYA
Hiroaki Furukawa
Yuhichi Saitoh

Assignees

Sharp Display Technology Corporation

Dates

Publication Date: 20260512
Application Date: 20240722

Claims (16)

1 . An active matrix substrate having a display region defined by a plurality of pixel regions arrayed along a first direction and a second direction perpendicular to the first direction, the active matrix substrate comprising: a substrate; a thin film transistor supported by the substrate, the thin film transistor including: a lower gate electrode provided on the substrate and made of a lower gate metal layer, a lower gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the lower gate insulating layer, the oxide semiconductor layer including a channel region opposing the lower gate electrode with the lower gate insulating layer interposed therebetween and a source contact region and a drain contact region located on respective sides of the channel region, an upper gate insulating layer provided on the channel region of the oxide semiconductor layer, and an upper gate electrode provided on the upper gate insulating layer, made of an upper gate metal layer, and opposing the channel region of the oxide semiconductor layer with the upper gate insulating layer interposed therebetween, a lower gate line extending in the first direction, made of the lower gate metal layer, and electrically coupled with the lower gate electrode, and an upper gate line extending in the first direction, made of the upper gate metal layer, and electrically coupled with the upper gate electrode, wherein a width of the upper gate line is greater than a width of the lower gate line, and the lower gate line overlaps with the upper gate line in a plan view.
2 . The active matrix substrate of claim 1 , wherein the upper gate line includes a first region, a second region, and a third region, the first region overlaps the lower gate line in a plan view, the second region and the third region do not overlap the lower gate line in a plan view.
3 . The active matrix substrate of claim 2 , wherein the first region is located between the second region and the third region.
4 . The active matrix substrate of claim 3 , wherein a width of each of the second region and the third region of the upper gate line is 0.5 μm or more.
5 . The active matrix substrate of claim 1 , wherein the thin film transistor is located in each of the plurality of pixel regions.
6 . The active matrix substrate of claim 1 , further comprising: a source line extends in the second direction.
7 . The active matrix substrate of claim 6 , wherein the thin film transistor further includes a source electrode electrically coupled with the source contact region of the oxide semiconductor layer; the source electrode and the source line are made of a source metal layer.
8 . The active matrix substrate of claim 7 , further comprising an interlayer insulating layer covering the upper gate electrode and the oxide semiconductor layer; wherein the source electrode and the source line are provided on the interlayer insulating layer.
9 . The active matrix substrate of claim 8 , wherein the interlayer insulating layer has a source contact hole, and the source electrode is electrically coupled with the source contact region of the oxide semiconductor layer via the source contact hole.
10 . The active matrix substrate of claim 1 , wherein a part of the lower gate line functions as the lower gate electrode.
11 . The active matrix substrate of claim 1 , wherein a part of the upper gate line functions as the upper gate electrode.
12 . The active matrix substrate of claim 1 , wherein the lower gate electrode and the upper gate electrode are electrically coupled with each other and supplied with an equal potential.
13 . The active matrix substrate of claim 1 , wherein the width of the upper gate line is greater than the width of the lower gate line by 1.0 μm or more.
14 . The active matrix substrate of claim 1 , wherein the oxide semiconductor layer includes an In—Ga—Zn—O based semiconductor.
15 . A display device comprising: the active matrix substrate as set forth in claim 1 .
16 . The active matrix substrate of claim 1 , wherein the upper gate line and the lower gate line extend across at least two of the plurality of pixel regions.

Description

BACKGROUND 1. Technical Field The present invention relates to an active matrix substrate and particularly to an active matrix substrate including oxide semiconductor TFTs. The present invention also relates to a liquid crystal display device including such an active matrix substrate. 2. Description of the Related Art In recent years, head-mounted displays (HMD) have increasingly higher display resolutions. Ultra-high resolution (e.g., 1000 ppi or higher) liquid crystal display devices for head-mounted displays are required to achieve a reduction in the size of a thin film transistor provided in each pixel (called “pixel TFT”) for the purpose of improving the aperture ratio. A possible solution to the above-described problem is to use an oxide semiconductor TFT as the pixel TFT. The oxide semiconductor TFT is TFT including an oxide semiconductor layer as an active layer. For example, Patent Document No. 1 (Japanese Laid-Open Patent Publication No. 2012-134475) discloses an oxide semiconductor TFT in which an In—Ga—Zn—O based semiconductor is used as the material of the active layer. When a transparent oxide semiconductor is used as the material of the active layer of the pixel TFT while metal electrodes and the like are omitted, the pixel TFT can be partially transparent, and thus, the aperture ratio can be improved. Note that the mobility of the oxide semiconductor is higher than that of amorphous silicon but is lower than that of polycrystalline silicon, such as LTPS (low-temperature polysilicon). Therefore, there is a limit to the reduction in the size of the oxide semiconductor TFT itself so long as charging of the pixels can be achieved at a sufficiently high rate. A possible solution to the size reduction without reduction of the ON current is to employ a “double-gate structure” in the oxide semiconductor TFT. In an oxide semiconductor TFT having the double-gate structure, a pair of gate electrodes are provided so as to sandwich the oxide semiconductor layer. Specifically, a gate electrode is provided under the oxide semiconductor layer (hereinafter, referred to as “lower gate electrode”) while another gate electrode is provided above the oxide semiconductor layer (hereinafter, referred to as “upper gate electrode”). An example of the double-gate structure oxide semiconductor TFT is disclosed in Patent Document No. 2 (Japanese Laid-Open Patent Publication No. 2016-184739). SUMMARY However, when the double-gate structure oxide semiconductor TFT is used, there is a concern that, as the display resolution further increases, the slope (level difference) which is attributed to two gate electrodes (i.e., two gate line layers) becomes larger as will be described later. If this slope (level difference) becomes larger, there is a probability that etching residues of the source metal (the metal material for formation of the source line) will occur on its side surface and cause leakage between lines. The present invention was conceived in view of the above-described problems. An object of the present invention is to suppress occurrence of etching residues of the source metal in an active matrix substrate including double-gate structure oxide semiconductor TFTs. This specification discloses an active matrix substrate and a liquid crystal display device as set forth in the following items. [Item 1] An active matrix substrate having a display region defined by a plurality of pixel regions arrayed in a matrix, the active matrix substrate comprising: a substrate;a thin film transistor supported by the substrate and located in a corresponding one of the plurality of pixel regions; anda pixel electrode electrically coupled with the thin film transistor,wherein the thin film transistor includes a lower gate electrode provided on the substrate,a lower gate insulating layer located so as to cover the lower gate electrode,an oxide semiconductor layer provided on the lower gate insulating layer, the oxide semiconductor layer including a channel region opposing the lower gate electrode with the lower gate insulating layer interposed therebetween and a source contact region and a drain contact region located at opposite sides of the channel region,an upper gate insulating layer provided on the channel region of the oxide semiconductor layer, andan upper gate electrode provided on the upper gate insulating layer and opposing the channel region of the oxide semiconductor layer with the upper gate insulating layer interposed therebetween, wherein the active matrix substrate includes a lower gate metal layer that includes the lower gate electrode and a lower gate line electrically coupled with the lower gate electrode, andan upper gate metal layer that includes the upper gate electrode and an upper gate line electrically coupled with the upper gate electrode, and wherein a width of the upper gate line is greater than a width of the lower gate line. [Item 2] The active matrix substrate as set forth