US-12625425-B2 - Lithography mask

US12625425B2US 12625425 B2US12625425 B2US 12625425B2US-12625425-B2

Abstract

A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Inventors

Chien-Cheng Chen
Huan-Ling Lee
Ta-Cheng Lien
Chia-Jen Chen
Hsin-Chang Lee

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20240103

Claims (20)

1 . A method of manufacturing a mask for use in a semiconductor lithography process performed using light at a lithography wavelength, the method comprising: providing a substrate coated with a light absorbing layer that is absorbing for the light at the lithography wavelength; and removing portions of the light absorbing layer to form a mask pattern and a light absorbing border on the substrate; wherein the light absorbing border surrounds the mask pattern, the light absorbing border comprising a portion of the light absorbing layer that is not removed; wherein the removing includes removing portions of the light absorbing layer on at least two opposite sides of the light absorbing border to define a peripheral region, wherein the light absorbing border extends to at least one edge of the substrate; and the removing includes: disposing a positive resist layer on the light absorbing layer; performing electron beam writing to expose portions of the positive resist layer corresponding to the portions of the light absorbing layer to be removed including performing the electron beam writing to expose the peripheral region; developing the positive resist layer after the electron beam writing to form openings in the positive resist corresponding to the portions of the light absorbing layer to be removed; and etching the portions of the light absorbing layer to be removed through the openings in the positive resist.
2 . The method of claim 1 wherein the peripheral region extends from an outer perimeter of the light absorbing border to an edge of the substrate.
3 . The method of claim 2 wherein a width of the peripheral region extending from the outer perimeter of the light absorbing border to the edge of the substrate is at least three times a width of the light absorbing border.
4 . The method of claim 1 wherein the peripheral region includes: a first peripheral region that extends from an outer perimeter of the light absorbing border to a first edge of the substrate; and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate; wherein the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.
5 . The method of claim 1 wherein an area of the peripheral region is at least twice an area of the light absorbing border.
6 . The method of claim 1 wherein: the removing forms one or more isolated light absorbing regions each surrounded by the peripheral region, the light absorbing layer not being removed in the one or more isolated light absorbing regions.
7 . The method of claim 1 wherein the lithography wavelength is 280 nm or smaller.
8 . The method of claim 1 wherein the substrate is light transmissive for the light at the lithography wavelength.
9 . The method of claim 1 wherein the light absorbing layer is a metal layer.
10 . The method of claim 1 wherein the light absorbing layer comprises chromium.
11 . The method of claim 10 wherein the substrate comprises quartz, titanium dioxide (TiO 2 ), or doped silicon dioxide (SiO 2 ).
12 . The method of claim 1 wherein the removing forms the mask pattern comprising absorbing pattern regions in which the light absorbing layer is not removed and non-absorbing regions in which the light absorbing layer is removed by the removing.
13 . The method of claim 12 further comprising: prior to the removing, performing an exposure/development cycle and an etch to produce a thickness variation of the light absorbing layer in the mask pattern; wherein the mask pattern comprises an attenuated phase shift mask (APSM) pattern in which a thickness of the light absorbing layer disposed in the absorbing pattern regions is not uniform.
14 . A semiconductor lithography method comprising: mounting a mask fabricated according to claim 1 on a mask stage wherein the peripheral region contacts support pads of the mask stage; performing semiconductor lithography using light at the lithography wavelength passing through the mask; and after performing the semiconductor lithography, removing the mask from the mask stage.
15 . A mask fabrication process comprising: providing a substrate coated with a light absorbing layer and a positive resist layer; and performing an exposure/development cycle and an etch step to remove portions of the light absorbing layer to define (i) non-absorbing pattern regions of a mask pattern surrounded by a light absorbing border, wherein the light absorbing border extends to at least one edge of the substrate, and (ii) a peripheral region outside of the light absorbing border in which the light absorbing layer is removed by the exposure/development cycle; wherein the exposure/development cycle includes performing electron beam writing to expose portions of the positive resist layer to be removed by the etch step including exposing the portions of the positive resist layer in both the non-absorbing pattern regions and the peripheral region.
16 . The mask fabrication process of claim 15 wherein the mask fabrication process is an attenuated phase shift mask (APSM) fabrication process that further comprises: a first exposure/development cycle and a first etch step performed before the exposure/development cycle, the first exposure/development cycle and the first etch step to produce a thickness variation of the light absorbing layer in the mask pattern.
17 . A method of manufacturing a mask for use in a semiconductor lithography process performed using light at a lithography wavelength, the method comprising: providing a substrate with a light absorbing layer disposed directly on the substrate that is absorbing for the light at the lithography wavelength; and removing portions of the light absorbing layer to form a mask pattern and a light absorbing border on the substrate; wherein the light absorbing border surrounds the mask pattern, the light absorbing border comprising a portion of the light absorbing layer that is not removed; wherein the removing includes removing portions of the light absorbing layer on at least two sides of the light absorbing border to define a peripheral region in which the substrate is exposed; and the removing includes: disposing a positive resist layer on the light absorbing layer; performing electron beam writing to expose portions of the positive resist layer corresponding to the portions of the light absorbing layer to be removed including performing the electron beam writing to expose the peripheral region; developing the positive resist layer after the electron beam writing to form openings in the positive resist corresponding to the portions of the light absorbing layer to be removed; and etching the portions of the light absorbing layer to be removed through the openings in the positive resist.
18 . The method of claim 17 , wherein a width of the peripheral region extending from the outer perimeter of the light absorbing border to the edge of the substrate is at least three times a width of the light absorbing border.
19 . The method of claim 17 , wherein the light absorbing layer comprises chromium.
20 . The method of claim 17 , wherein the substrate comprises quartz, titanium dioxide (TiO 2 ), or doped silicon dioxide (SiO 2 ).

Description

This application is a continuation of U.S. application Ser. No. 17/321,852 filed May 17, 2021, now U.S. Pat. No. 11,899,357, which is incorporated herein by reference in its entirety. BACKGROUND The following relates to semiconductor manufacturing, masks for use in semiconductor lithography processes, lithography mask fabrication methods, deep ultraviolet (UV) semiconductor lithography, and to related arts. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 diagrammatically illustrates a lithography system including a lithography mask. FIG. 2 diagrammatically illustrates a plan view of a lithography mask. FIG. 3 diagrammatically illustrates the plan view of the lithography mask of FIG. 2, with the support pads of a mask stage diagrammatically indicated. FIG. 4 diagrammatically illustrates a plan view of a lithography mask with a reduced light-absorbing border. FIG. 5 diagrammatically illustrates the plan view of the lithography mask of FIG. 4 with the reduced light-absorbing border, with the support pads of a mask stage diagrammatically indicated. FIG. 6 diagrammatically illustrates a mask fabrication method. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. With reference to FIG. 1, a non-limiting illustrative semiconductor lithography apparatus is diagrammatically shown, which includes a light source system 10, a mask stage 12 (also sometimes called a reticle stage 12 or other similar nomenclature), an imaging system 14, and a wafer stage 16. The semiconductor lithography is performed using light L generated by the light source system 10 at a lithography wavelength that is chosen based on factors such as the feature size to be lithographically transferred from a mask 20 (also sometimes called a reticle 20 or similar nomenclature) mounted on the mask stage 12 to a semiconductor wafer 22 mounted on the wafer stage 16. For example, the lithography process could employ light L in the visible wavelength range, in which case the lithography wavelength is in the range of 400-700 nm (corresponding to a photon energy range of 1.77 eV to 3.10 eV), or ultraviolet (UV) light in which the lithography wavelength is below 400 nm (corresponding to a photon energy greater than 3.10 eV). In some non-limiting illustrative embodiments, the lithography process is a deep UV semiconductor lithography process, for example using a lithography wavelength of 193 nm in one non-limiting illustrative example, or using a lithography wavelength of 248 nm in another non-limiting illustrative example. In some non-limiting illustrative embodiments, the lithography wavelength is 280 nm or smaller. The light source system 10 includes a light source suitable for generating light L at the design-basis lithography wavelength. As a non-limiting example, for deep UV semiconductor lithography at 193 nm an excimer laser with argon fluoride (ArF) is a suitable light source. As another non-limiting example, for deep UV semiconductor lithography at 248 nm an excimer laser with krypton fluoride (KrF) is a suitable light source. The light source system 10 optionally al