US-12625434-B2 - Lithography scanner throughput

US12625434B2US 12625434 B2US12625434 B2US 12625434B2US-12625434-B2

Abstract

A method and system for optimizing scan speed of a lithography scanner. A process design layout corresponding to a plurality of rows of fields to be formed on an associated wafer is received and a default machine constant of the lithography scanner is determined. Each of the plurality of rows is then identified corresponding to the received process design layout. A scan speed for each determined type of row and the determined default machine constant is then determined. The associated wafer is then processed utilizing the determined scan speed for each of the plurality of rows in accordance with the process design layout.

Inventors

Kai-Chieh Chang
Che-Chang Hsu
Kai-Fa Ho
Li-Jui Chen

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20231117

Claims (20)

1 . A method for optimizing scan speed for increased throughput in a lithography device, the lithography device including a reticle assembly stage and a wafer assembly stage, the method comprising: receiving a process design layout corresponding to a plurality of fields to be formed on an associated wafer; determining a full field scan length in accordance with the received process design layout; determining a default machine constant including determining a movement speed of the reticle assembly stage and determining a movement speed of the wafer assembly stage; identifying a type of each of a plurality of rows of fields corresponding to the received process design layout, wherein the type of row of field is selected from a group including a center fields row, an edge fields row, or an edge and center field combined row; determining a center field row scan speed for each of the plurality of rows identified as a center fields row; determining an edge field row scan speed for each of the plurality of rows identified as an edge fields row; determining an edge and center field combined row scan speed for each of the plurality of rows identified as an edge and center field combined row, wherein the edge and center field combined row scan speed utilizes the center field row scan speed for each center field in the edge and center field combined row and the edge field scan speed for each edge field in the edge and center field combined row; and processing the associated wafer utilizing the center field row scan speed, the edge field scan speed, and the edge and center field combined scan speed in accordance with the process design layout; wherein each center field is the full scan length and each edge field has a scan length less than the full scan length; wherein determining the center field row scan speed, the edge field scan speed, and the edge and center field combined scan speed is performed in accordance with the default machine constant; and wherein determining the center field row scan speed further comprises differentiating a scan time of the lithography device and an acceleration time of the reticle stage assembly.
2 . The method of claim 1 wherein determining the edge field row scan speed further comprises determining an exposure time, a scan length and a step time.
3 . The method of claim 1 , wherein the lithography device is an extreme ultraviolet lithography (EUV) device.
4 . A method for optimizing scan speed of a lithography scanner device, the lithography scanner device including a reticle assembly stage and a wafer assembly stage, the method comprising: receiving a process design layout corresponding to a plurality of rows of fields to be formed on an associated wafer; determining a default machine constant of the lithography scanner; identifying a type of each of the plurality of rows of fields corresponding to the received process design layout, wherein the type of row of field is selected from a group including a center fields row, an edge fields row, or an edge and center field combined row; determining a scan speed in accordance with the determined type of row and the determined default machine constant; and processing the associated wafer utilizing the determined scan speed for each of the plurality of rows in accordance with the process design layout; wherein determining a center field row scan speed further comprises differentiating a scan time of the lithography scanner device and an acceleration time of the reticle stage assembly.
5 . The method of claim 4 , wherein determining the default machine constant comprises: determining a movement speed of the reticle assembly stage; and determining a movement speed of the wafer assembly stage.
6 . The method of claim 4 , wherein determining a scan speed further comprises: determining the center field row scan speed for each of the plurality of rows identified as a center fields row; determining an edge field row scan speed for each of the plurality of rows identified as an edge fields row; and determining an edge and center field combined row scan speed for each of the plurality of rows identified as an edge and center field combined row, wherein the edge and center field combined row scan speed utilizes the center field row scan speed for each center field in the edge and center field combined row and the edge field scan speed for each edge field in the edge and center field combined row.
7 . The method of claim 6 , wherein determining the center field row scan speed, the edge field scan speed, and the edge and center field combined scan speed is performed in accordance with the default machine constant.
8 . The method of claim 7 , wherein the determined edge field row scan speed is less than or equal to the center field row scan speed in accordance with a scan length and the default machine constant.
9 . The method of claim 4 , wherein each center field is a full scan length and each edge field has a scan length less than a full scan length.
10 . The method of claim 4 , wherein determining the edge field row scan speed further comprises determining an exposure time, a scan length, and a step time.
11 . The method of claim 4 , wherein the lithography scanner device is an extreme ultraviolet lithography (EUV) device.
12 . The method of claim 4 , wherein determining the default machine constant comprises retrieving the default machine constant from a database.
13 . A system for optimizing scan speed of a lithographic scanner device, the system comprising: a reticle stage assembly, comprising a reticle and at least one motor for movement in the x-direction and the y-direction; a wafer stage assembly, comprising a wafer stage body and a wafer retention component configured to hold a wafer thereon; and a controller comprising a processor in communication with memory storing instructions which are executed by the processor to: receive a process design layout corresponding to a plurality of fields to be formed on the wafer, identify, via a field identification component, each of the plurality of fields as a center field or an edge field, determine, via a scan speed determination component; a center field row scan speed for each of a plurality of rows identified as a center fields row; an edge field row scan speed for each of a plurality of rows identified as an edge fields row; an edge and center field combined row scan speed for each of a plurality of rows identified as an edge and center field combined row, wherein the edge and center field combined row scan speed utilizes the center field row scan speed for each center field in the edge and center field combined row and the edge field scan speed for each edge field in the edge and center field combined row; and an optimum scan speed for each field in the plurality of fields in accordance with the identified field type and a default machine constant, wherein determining an optimum scan speed for the center field comprises differentiating a scan time of the lithographic scanner device and an acceleration time of the reticle stage assembly, and activate, via a motor control component, the at least one motor in accordance with the determined optimum scan speed for each of the plurality of fields.
14 . The system of claim 13 , wherein the memory further stores instructions to determine the default machine constant.
15 . The system of claim 14 , wherein the default machine constant corresponds to a movement speed of the reticle assembly stage, and a movement speed of the wafer assembly stage.
16 . The system of claim 13 , wherein each of the center field row scan speed, the edge field row scan speed and the edge and center field combined row scan speed are determined in accordance with the default machine constant.
17 . The system of claim 16 , wherein the determined edge field row scan speed is less than or equal to the center field row scan speed in accordance with a field size and the default machine constant.
18 . The system of claim 13 , wherein each center field is the full scan length and each edge field has a scan length less than a full scan length.
19 . The system of claim 13 , wherein determining the edge field row scan speed further comprises determining an exposure time, a scan length, and a step time.
20 . The system of claim 13 , wherein the lithographic scanner device is an extreme ultraviolet lithography (EUV) device.

Description

BACKGROUND A lithographic apparatus is a machine that utilizes a reticle (i.e., photomask) that applies a desired pattern onto a target portion of a substrate. The reticle may be a reflective mask or a transmission mask. In the process, ultraviolet light is reflected off the surface of the reticle (for a reflective mask) or transmitted through the reticle (for a transmission mask) to transfer the pattern to a photoresist onto a target portion of a semiconductor wafer. The minimum feature size of the pattern is limited by the light wavelength. Deep ultraviolet (UV) lithography uses a wavelength of 193 nm or 248 nm. Extreme ultraviolet (EUV) light, which spans wavelengths from 124 nanometers (nm) down to 10 nm, is currently being used to provide small minimum feature sizes. A lithographic scanner is one type of such apparatus, in which each target portion is exposed by scanning the reticle through a projection beam in a given direction, while simultaneously scanning (i.e. moving) the wafer substrate parallel or anti-parallel to this direction. The scanning speed of the scanner affects not only quality but also throughput. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic view of a lithography system in accordance with some embodiments. FIG. 2A is a side view of a reticle stage assembly used in the lithography system of FIG. 1 in accordance with some embodiments. FIG. 2B is a bottom view of a reticle stage assembly used in the lithography system of FIG. 1 in accordance with some embodiments. FIG. 3 is a side view of a wafer stage assembly used in the lithography system of FIG. 1 in accordance with some embodiments. FIG. 4 illustrates a block diagram of a controller in accordance with some embodiments. FIG. 5 is a flowchart illustrating a method for optimizing scan speed of a lithography scanner in accordance with some embodiments. FIG. 6 is an illustrative example of a wafer scan down/scan up routing in accordance with some embodiments. FIGS. 7A-7C are a simplified illustrative example of fields on a wafer in accordance with some embodiments. FIG. 8 is an illustrative graph of scan speeds in accordance with some embodiments. FIGS. 9A-9B provide simplified representations of scanning time and step time in accordance with some embodiments. FIGS. 10A-10C provide an illustrative view of the difference in scan lengths in accordance with some embodiments. FIG. 11 is a flowchart illustrating a method for optimizing scan speed of a lithography scanner in accordance with some embodiments. FIGS. 12A-12B are comparative examples of output performance in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Numerical values in the specification and claims of this application should be understood to include numerical values which are the same when reduced to the same number of significant figures and numerical values which differ from the stated value by less than the experimental error of conventional measurement technique of the type described in the present application to determine the valu