US-12625440-B2 - Semiconductor structure body and method for manufacturing semiconductor structure body with alignment between stories of the same

US12625440B2US 12625440 B2US12625440 B2US 12625440B2US-12625440-B2

Abstract

A semiconductor structure body of an embodiment includes a stacked body. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked, and a plurality of through holes penetrating the conductive layers and the insulating layers in the stacking direction are provided. In the interior of the stacked body, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks are formed, with one or more stories each including a predetermined number of conductive layers and a predetermined number of insulating layers interposed therebetween.

Inventors

Manabu Takakuwa

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20230313
Priority Date: 20220620

Claims (8)

1 . A semiconductor structure body comprising a stacked body with multiple stories in each of which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a plurality of through holes penetrating the conductive layers and the insulating layers in a stacking direction, wherein, the multiple stories of the stacked body is four stories or more, the stacked body includes, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks, and the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a first pair of coordinates on an uppermost surface of an N-th story (N is an integer equal to or larger than 2) of the multiple stories and a region corresponding to the first pair of coordinates on an uppermost surface of an (N+2)-th story of the multiple stories.
2 . The semiconductor structure body according to claim 1 , wherein the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a second pair of coordinates on an uppermost surface of an (N+1)-th story of the multiple stories and a region corresponding to the second pair of coordinates on an uppermost surface of an (N+3)-th story of the multiple stories.
3 . The semiconductor structure body according to claim 1 , wherein the identical alignment marks or the deviation measurement marks are each formed by a process in which a level difference formed by reducing a thickness of at least one of the conductive layer and the insulating layer propagates to an uppermost surface of the respective story, and a width of the level difference is 1 μm or more and 4 μm or less.
4 . The semiconductor structure body according to claim 1 , comprising: a plurality of chip regions; and a dicing region formed to surround a periphery of each of the chip regions, wherein the identical alignment marks or the deviation measurement marks are each placed in the dicing region.
5 . The semiconductor structure body according to claim 4 , wherein the identical alignment marks are each placed in a central portion of a shot region including the plurality of chip regions, or the deviation measurement marks are each placed in an outer edge portion of the shot region.
6 . The semiconductor structure body according to claim 4 , wherein a three-dimensional stacked semiconductor memory device is formed in the chip region.
7 . A semiconductor structure body comprising a stacked body with multiple stories in each of which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a plurality of through holes penetrating the conductive layers and the insulating layers in a stacking direction, wherein, the multiple stories of the stacked body is five stories or more, the stacked body includes, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks, and the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a first pair of coordinates on an uppermost surface of an N-th story (N is an integer equal to or larger than 2) of the multiple stories and a region corresponding to the first pair of coordinates on an uppermost surface of an (N+3)-th story of the multiple stories.
8 . The semiconductor structure body according to claim 7 , wherein the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a second pair of coordinates on an uppermost surface of an (N+1)-th story of the multiple stories and a region corresponding to the second pair of coordinates on an uppermost surface of an (N+4)-th story of the multiple stories, and the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a third pair of coordinates on an uppermost surface of an (N+2)-th story of the multiple stories and a region corresponding to the third pair of coordinates on an uppermost surface of an (N+5)-th story of the multiple stories.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-098523, filed on Jun. 20, 2022; the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor structure body and a method for manufacturing a semiconductor structure body. BACKGROUND A three-dimensional stacked semiconductor memory device in which a plurality of memory cells are three-dimensionally arranged in a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked is used. In such a semiconductor memory device, an increase in the number of stacked layers of the stacked body is required in order to increase the storage capacity. As a technique for achieving an increase in the number of stacked layers, there is a technique of dividing a stacked body into a plurality of stories and forming stacked bodies in stages for stories. In the case where stacked bodies are thus formed in stages, the processing of alignment between stories is needed, but conventional technology has problems of an increase in cost, a reduction in working efficiency, etc. because a mask for forming an alignment mark needs to be prepared for each story. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view illustrating an example of a configuration of a wafer of an embodiment; FIG. 2 is a plan view illustrating an example of a configuration of a shot region of the embodiment; FIG. 3 is a cross-sectional view illustrating an example of a configuration of a stacked body formed in a chip region of the embodiment; FIG. 4 is a plan view illustrating an example of an exposure alignment mark of the embodiment; FIG. 5 is a plan view illustrating an example of a deviation measurement mark of the embodiment; FIG. 6 is a plan view illustrating an example of a structure of a first mask of the embodiment; FIG. 7 is a plan view illustrating an example of a structure of a second mask of the embodiment; FIG. 8 is a flowchart illustrating an example of part of processing in a method for manufacturing a semiconductor memory device of the embodiment; FIG. 9A is a cross-sectional view illustrating an example of a state of a first story, a first hard mask layer, and a first resist pattern in a first exposure alignment region of the embodiment; FIG. 9B is a cross-sectional view illustrating an example of a state of the first story after processing with the first resist pattern in the first exposure alignment region of the embodiment; FIG. 9C is a cross-sectional view illustrating an example of exposure alignment level differences of the first story of the embodiment; FIG. 9D is a cross-sectional view illustrating an example of a state of a second story in the first exposure alignment region of the embodiment; FIG. 9E is a cross-sectional view illustrating an example of a state of the second story, a second hard mask layer, and a second resist pattern in the first exposure alignment region of the embodiment; FIG. 9F is a cross-sectional view illustrating an example of a state of the second story after processing with the second resist pattern in the first exposure alignment region of the embodiment; FIG. 9G is a cross-sectional view illustrating an example of a state of a third story in the first exposure alignment region of the embodiment; FIG. 9H is a cross-sectional view illustrating an example of a state of the third story, a third hard mask layer, and the first resist pattern in the first exposure alignment region of the embodiment; FIG. 9I is a cross-sectional view illustrating an example of a state of the third story after processing with the first resist pattern in the first exposure alignment region of the embodiment; FIG. 9J is a cross-sectional view illustrating an example of exposure alignment level differences of the third story of the embodiment; FIG. 9K is a cross-sectional view illustrating an example of a configuration of a stacked body in the first exposure alignment region of the embodiment; FIG. 10A is a cross-sectional view illustrating an example of a state of the first story, the first hard mask layer, and the first resist pattern in a first deviation measurement region of the embodiment; FIG. 10B is a cross-sectional view illustrating an example of a state of the first story after processing with the first resist pattern in the first deviation measurement region of the embodiment; FIG. 10C is a cross-sectional view illustrating an example of deviation measurement level differences of the first story of the embodiment; FIG. 10D is a cross-sectional view illustrating an example of a state of the second story in the first deviation measurement region of the embodiment; FIG. 10E is a cross-sectional view illustrating an example of a state of the second story, the second hard mask layer, and the second resist pattern in the first deviation measurement region of