US-12625511-B2 - In situ strain compensation AFE

US12625511B2US 12625511 B2US12625511 B2US 12625511B2US-12625511-B2

Abstract

A circuit ( 70 ) includes a voltage reference circuit ( 72 ) that includes an output terminal ( 74 ), wherein the voltage reference circuit ( 72 ) is configured to generate an output voltage at the output terminal ( 74 ) having a first transfer function of voltage with respect to strain. The circuit ( 70 ) also includes a strain compensation circuit ( 78 ) having an input terminal connected to the output terminal ( 74 ) of the voltage reference circuit, and having a strain compensation circuit output terminal ( 80 ). The strain compensation circuit ( 78 ) is configured to receive the output voltage comprising the first transfer function at the input terminal. The strain compensation circuit ( 78 ) has a second transfer function of voltage with respect to strain that is substantially opposite that of the first transfer function, thereby outputting a compensated voltage at the strain compensation circuit output terminal ( 80 ) that is substantially independent of strain.

Inventors

Divya Kaur
Vinod Menezes

Assignees

TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20231222
Priority Date: 20230720

Claims (20)

1 . A circuit, comprising: a voltage reference circuit having an output, in which a voltage at the output of the voltage reference circuit varies with stress in a first direction; and a circuit coupled between the output of the voltage reference circuit and a reference output, in which an impedance of the circuit varies with stress in a second direction opposite from the first direction.
2 . The circuit of claim 1 , wherein the circuit comprises a piezoelectric resistor.
3 . The circuit of claim 1 , further comprising: a variable current source circuit coupled to the reference output.
4 . The circuit of claim 3 , further comprising: a current generation circuit configurable to generate a first current; and wherein the variable current source circuit is coupled to the current generation circuit, and further configured to receive the first current and source or sink a second current at the reference output and through the circuit responsive to the first current.
5 . The circuit of claim 4 , wherein the variable current source circuit comprises: a plurality of parallel-connected, selectively activated transistor circuits coupled in a current mirror configuration with the current generation circuit; and a control circuit configurable to generate and couple a plurality of control signals to the parallel-connected, selectively activated transistor circuits, respectively, thereby causing one or more of the parallel-connected, selectively activated transistor circuits to conduct to source or sink the second current.
6 . The circuit of claim 5 , wherein each parallel-connected, selectively activated transistor circuit comprises a transistor connected in series with a switch element that is configurable to receive a respective one of the plurality of control signals at a control terminal thereof, wherein when a state of the respective control signal closes the switch element, the respective parallel-connected, selectively activated transistor circuit is activated and conducts a current therethrough having a magnitude corresponding to a sizing of the respective transistor.
7 . The circuit of claim 3 , further comprising: a temperature compensation circuit coupled between the circuit and the reference output, the temperature compensation circuit configurable to provide an offset voltage responsive to a temperature.
8 . The circuit of claim 1 , wherein the voltage reference circuit includes a Zener diode.
9 . A circuit comprising: a voltage reference circuit having an output; a resistor coupled between the output and a reference output; and a programmable current source coupled to the reference output configurable to inject or sink a current at the reference output via the resistor.
10 . The circuit of claim 9 , wherein the resistor has an impedance that is a function of strain.
11 . The circuit of claim 10 , wherein the resistor is a piezoelectric resistor.
12 . The circuit of claim 9 , wherein the programmable current source is a first current source, and the circuit further comprises a second current source coupled to the first current source.
13 . The circuit of claim 12 , wherein the first current source comprises: a plurality of parallel-connected, selectively activated transistor circuits coupled in a current mirror configuration with circuitry in the second current source; and a control circuit configurable to generate and couple a plurality of control signals to the parallel-connected, selectively activated transistor circuits, respectively, thereby causing one or more of the parallel-connected, selectively activated transistor circuits to conduct.
14 . The circuit of claim 13 , wherein each parallel-connected, selectively activated transistor circuit comprises a transistor connected in series with a switch circuit element that is configured to receive a respective one of the plurality of control signals at a control terminal thereof, wherein when a state of the respective control signal closes the switch circuit element, the respective parallel-connected, selectively activated transistor circuit is activated and conducts a current therethrough having a magnitude corresponding to a sizing of the respective transistor.
15 . The circuit of claim 9 , further comprising: a temperature compensation circuit coupled between the circuit and the reference output, the temperature compensation circuit configurable to provide an offset voltage responsive to a temperature.
16 . The circuit of claim 9 , wherein the voltage reference circuit includes a Zener diode.
17 . A method comprising: generating a first voltage, in which the first voltage varies with stress in a first direction; generating a second voltage, in which the second voltage varies with stress in a second direction opposite to the first direction; and generating a third voltage responsive to the first and second voltages.
18 . The method of claim 17 , wherein the second voltage is generated with a resistor.
19 . The method of claim 18 , further comprising: sourcing or sinking a current via the resistor to generate the second.
20 . The method of claim 18 , wherein generating a third voltage responsive to the first and second voltages includes generating the third voltage responsive to a summation of the first and second voltages, or generating the third voltage responsive to a difference between the first and second voltages.

Description

REFERENCE TO RELATED APPLICATION This Application claims the benefit of Indian Patent Application No. 202341048797, filed on Jul. 20, 2023, the contents of which are hereby incorporated by reference in their entirety. BACKGROUND Many modern devices include various electrical circuits. One type of circuit is a voltage reference circuit. It is desired to make a voltage reference circuit that is precise and to maintain such precision over time and independent of stress, temperature, or both. SUMMARY In one example, a circuit comprises a voltage reference circuit comprising an output terminal. The voltage reference circuit is configured to generate an output voltage at the output terminal, and the output voltage comprises a first transfer function of voltage with respect to strain. The circuit also comprises a strain compensation circuit having an input terminal connected to the output terminal of the voltage reference circuit, and having a strain compensation circuit output terminal. The strain compensation circuit is configured to receive the output voltage comprising the first transfer function at the input terminal. The strain compensation circuit comprises a second transfer function of voltage with respect to strain that is substantially opposite that of the first transfer function, thereby outputting a compensated voltage at the strain compensation circuit output terminal that is substantially independent of strain. In one aspect of the disclosure the strain compensation circuit comprises a strain dependent circuit element that exhibits an impedance that is a function of strain. Further, in one aspect of the disclosure the strain dependent circuit element comprises a piezoelectric resistor. The circuit, in another aspect of the disclosure, further comprises a variable current source circuit connected to the strain compensation circuit output terminal. The variable current source circuit is configured to source or sink a strain compensation current to or from, respectively, the strain compensation circuit. The strain compensation current results in a strain compensation voltage that the strain compensation circuit adds or subtracts, respectively, to the output voltage at the output terminal of the voltage reference circuit to form the compensated voltage at the strain compensation circuit output terminal. In another aspect of the disclosure, the circuit also comprises a baseline compensation current generation circuit configured to generate a baseline compensation current. The variable current source circuit is coupled to the baseline compensation current generation circuit, and is further configured to generate the strain compensation current based on the baseline compensation current. In one aspect of the disclosure the variable current source circuit comprises a plurality of parallel-connected, selectively activated transistor circuits coupled in a current mirror configuration with the baseline compensation circuit generation circuit. The variable current source circuit also comprises a control circuit configured to generate and couple a plurality of control signals to the parallel-connected, selectively activated transistor circuits, respectively, thereby causing one or more of the parallel-connected, selectively activated transistor circuits to conduct to form the strain compensation current. In one aspect of the disclosure, each parallel-connected, selectively activated transistor circuit comprises a transistor connected in series with a switch element that is configured to receive a respective one of the plurality of control signals at a control terminal thereof. When a state of the respective control signal closes the switch element, the respective parallel-connected, selectively activated transistor circuit is activated and conducts a current therethrough having a magnitude corresponding to a sizing of the respective transistor. In one aspect of the disclosure the circuit further comprises a temperature compensation circuit having an input terminal connected to the strain compensation circuit output terminal. The temperature compensation circuit is configured to sense a temperature at the circuit and generate a temperature compensation voltage based on the sensed temperature. The temperature compensation circuit is further configured to combine the temperature compensation voltage with the compensated voltage at the output terminal of the strain compensation circuit to form a combined strain and temperature compensated voltage at an output terminal of the temperature compensation circuit. In one aspect of the disclosure a circuit is disclosure that comprises a current source circuit configured to generate a source current at a current source output terminal. The source current has a first, bias current component, and a second, compensation current component. The circuit also comprises a voltage reference circuit configured to generate a reference voltage at a voltage reference output terminal. The