US-12625513-B2 - Duty correction circuit, a clock generation circuit and a semiconductor apparatus using the duty correction circuit

US12625513B2US 12625513 B2US12625513 B2US 12625513B2US-12625513-B2

Abstract

A duty correction circuit includes a first delay circuit, a second delay circuit, a dividing circuit, a duty detection circuit, and a delay control signal generation circuit. The first delay circuit is configured to delay a clock signal to generate a first delayed clock signal. The second delay circuit is configured to delay the clock signal based on a delay control signal to generate a second delayed clock signal. The dividing circuit is configured to divide the first and second delayed clock signals to generate a first to fourth phase clock signals. The duty detection circuit is configured to detect phases of the first to fourth phase clock signals to generate a duty detection signal. The delay control signal generation circuit generates the delay control signal based on the duty detection signal.

Inventors

Young Ouk Kim

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260512
Application Date: 20240126
Priority Date: 20230920

Claims (16)

1 . A duty correction circuit comprising: a first delay circuit configured to receive a clock signal and delay the clock signal to generate a first delayed clock signal; a second delay circuit configured to receive the clock signal and variably delay the clock signal based on a delay control signal to generate a second delayed clock signal; a dividing circuit configured to divide the first delayed clock signal to generate a first phase clock signal and a third phase clock signal, and configured to divide the second delayed clock signal to generate a second phase clock signal and a fourth phase clock signal; a duty detection circuit configured to gate the first to fourth phase clock signals to generate a plurality of gating clock signals, and configured to generate a duty detection signal based on the plurality of gating clock signals; and a delay control signal generation circuit configured to generate the delay control signal based on the duty detection signal.
2 . The duty correction circuit of claim 1 , wherein the first phase clock signal is synchronized to odd rising edges of the first delayed clock signal, and the third phase clock signal is synchronized to even rising edges of the first delayed clock signal, and wherein the second phase clock signal is synchronized to odd falling edges of the second delayed clock signal, and the fourth phase clock signal is synchronized to even falling edges of the second delayed clock signal.
3 . The duty correction circuit of claim 1 , wherein the dividing circuit comprises: a first divider configured to divide the first delayed clock signal to generate the first phase clock signal and the third phase clock signal; and a second divider configured to divide the second delayed clock signal to generate the second phase clock signal and the fourth phase clock signal.
4 . The duty correction circuit of claim 3 , wherein the first divider comprises: a first inverter configured to invert the first phase clock signal; a second inverter configured to invert an output signal of the first inverter; a first flip-flop configured to output the output signal of the first inverter as the first phase clock signal in synchronization with the first delayed clock signal; and a second flip-flop configured to output an output signal of the second inverter as the third phase clock signal in synchronization with the first delayed clock signal.
5 . The duty correction circuit of claim 3 , wherein the second divider comprises: a first inverter configured to invert the second delayed clock signal; a second inverter configured to invert the second phase clock signal; a third inverter configured to invert an output signal of the second inverter; a first flip-flop configured to output the output signal of the second inverter as the second phase clock signal in synchronization with an output signal of the first inverter; and a second flip-flop configured to output an output signal of the third inverter as the fourth phase clock signal in synchronization with the output signal of the first inverter.
6 . The duty correction circuit of claim 1 , wherein the duty detection circuit comprises: a clock gating circuit configured to gate the first phase clock signal to generate a first gating clock signal and a second gating clock signal, configured to gate the second phase clock signal to generate a third gating clock signal and a fourth gating clock signal, configured to gate the third phase clock signal to generate a fifth gating clock signal and a sixth gating clock signal, and configured to gate the fourth phase clock signal to generate a seventh gating clock signal and an eighth gating clock signal; and a duty detector configured to generate a first output signal and a second output signal based on the first to eighth gating clock signals, and configured to compare the first output signal and the second output signal to generate the duty detection signal.
7 . The duty correction circuit of claim 6 , wherein the duty detector is configured to change a voltage level of the first output signal based on the second gating clock signal, the third gating clock signal, the sixth gating clock signal, and the seventh gating clock signal, and configured to change a voltage level of the second output signal based on the first gating clock signal, the fourth gating clock signal, the fifth gating clock signal, and the eighth gating clock signal.
8 . The duty correction circuit of claim 6 , wherein the duty detector comprises: a first output node to which a first voltage is applied; a second output node to which the first voltage is applied; a first capacitor coupled between the first output node and a terminal to which a second voltage is supplied, and the first output signal being output from the first output node; a second capacitor coupled between the second output node and the terminal to which the second voltage is supplied, and the second output signal being output from the second output node; a first discharge circuit configured to discharge the first output node when the second gating clock signal and the seventh gating clock signal have a high logic level and when the third gating clock signal and the sixth gating clock signal have a high logic level; a second discharge circuit configured to discharge the second output node when the first gating clock signal and the fourth gating clock signal have a high logic level and when the fifth gating clock signal and the eighth gating clock signal have a high logic level; and a comparator configured to compare voltage levels of the first and second output signals to generate the duty detection signal.
9 . A clock generation circuit comprising: a phase delay circuit configured to receive a reference clock signal and delay the reference clock signal to generate a delay-locked clock signal; a first delay circuit configured to receive the delay-locked clock signal and delay the delay-locked clock signal to generate a first delayed clock signal; a second delay circuit configured to receive the delay-locked clock signal and variably delay the delay-locked clock signal to generate a second delayed clock signal based on a delay control signal; a dividing circuit configured to divide the first delayed clock signal to generate a first phase clock signal and a third phase clock signal, and configured to divide the second delayed clock signal to generate a second phase clock signal and a fourth phase clock signal; a clock gating circuit configured to gate the first to fourth phase clock signals to generate a first gating clock signal, a second gating clock signal, a third gating clock signal, a fourth gating clock signal, a fifth gating clock signal, a sixth gating clock signal, a seventh gating clock signal, and an eighth gating clock signal; a duty detector configured to generate a first output signal and a second output signal based on the first to eighth gating clock signals, and configured to compare the first and second output signals to generate a duty detection signal; and a delay control signal generation circuit configured to generate the delay control signal based on the duty detection signal.
10 . The clock generation circuit of claim 9 , wherein the first phase clock signal is synchronized to odd rising edges of the first delayed clock signal, and the third phase clock signal is synchronized to even rising edges of the first delayed clock signal, and wherein the second phase clock signal is synchronized to odd falling edges of the second delayed clock signal, and the fourth phase clock signal is synchronized to even falling edges of the second delayed clock signal.
11 . The clock generation circuit of claim 9 , wherein the dividing circuit comprises: a first divider configured to divide the first delayed clock signal to generate the first phase clock signal and the third phase clock signal; and a second divider configured to divide the second delayed clock signal to generate the second phase clock signal and the fourth phase clock signal.
12 . The clock generation circuit of claim 11 , wherein the first divider comprises: a first inverter configured to invert the first phase clock signal; a second inverter configured to invert an output signal of the first inverter; a first flip-flop configured to output the output signal of the first inverter as the first phase clock signal in synchronization with the first delayed clock signal; and a second flip-flop configured to output an output signal of the second inverter as the third phase clock signal in synchronization with the first delayed clock signal.
13 . The clock generation circuit of claim 11 , wherein the second divider comprises: a first inverter configured to invert the second delayed clock signal; a second inverter configured to invert the second phase clock signal; a third inverter configured to invert an output signal of the second inverter; a first flip-flop configured to output the output signal of the second inverter as the second phase clock signal in synchronization with an output signal of the first inverter; and a second flip-flop configured to output an output signal of the third inverter as the fourth phase clock signal in synchronization with the output signal of the first inverter.
14 . The clock generation circuit of claim 9 , wherein the clock gating circuit is configured to gate the first phase clock signal to generate the first gating clock signal and the second gating clock signal, configured to gate the second phase clock signal to generate the third gating clock signal and the fourth gating clock signal, configured to gate the third phase clock signal to generate the fifth gating clock signal and the sixth gating clock signal, and configured to gate the fourth phase clock signal to generate the seventh gating clock signal and the eighth gating clock signal.
15 . The clock generation circuit of claim 9 , wherein the duty detector is configured to change a voltage level of the first output signal based on the second gating clock signal, the third gating clock signal, the sixth gating clock signal, and the seventh gating clock signal, and configured to change a voltage level of the second output signal based on the first gating clock signal, the fourth gating clock signal, the fifth gating clock signal, and the eighth gating clock signal.
16 . The clock generation circuit of claim 9 , wherein the duty detector comprises: a first output node to which a first voltage is applied; a second output node to which the first voltage is applied; a first capacitor coupled between the first output node and a terminal to which a second voltage is supplied, and the first output signal being output from the first output node; a second capacitor coupled between the second output node and the terminal to which the second voltage is supplied, and the second output signal being output from the second output node; a first discharge circuit configured to discharge the first output node when the second gating clock signal and the seventh gating clock signal have a high logic level and when the third gating clock signal and the sixth gating clock signal are at a high logic level; a second discharge circuit configured to discharge the second output node when the first gating clock signal and the fourth gating clock signal have a high logic level and when the fifth gating clock signal and the eighth gating clock signal are at a high logic level; and a comparator configured to compare voltage levels of the first and second output signals to generate the duty detection signal.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2023-0125507 filed on Sep. 20, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. BACKGROUND 1. Technical Field Various embodiments generally relate to integrated circuit technology, and, more particularly, to a duty correction circuit, a clock generation circuit, and a semiconductor apparatus using the duty correction circuit. 2. Related Art An electronic device includes a lot of electronic elements and a computer system as the electronic device includes lots of semiconductor apparatuses each configured by semiconductor devices. A semiconductor apparatus constituting a computer system can communicate with each other by transmitting and receiving system clock signal, such as an external clock signal, and data. The semiconductor apparatus may operate in synchronization with a clock signal. The semiconductor apparatus may generate an internal clock signal from the system clock signal to match operation timing with an external device or to secure an operation margin, and may be equipped with a clock generation circuit for generating the internal clock signal. The clock generation circuit may generate the internal clock signal by changing a phase of the system clock signal or by dividing a frequency of the system clock signal. Further, the clock generation circuit may generate a plurality of internal clock signals having different phases. The clock generation circuit may have a plurality of clock paths to generate the plurality of internal clock signals. For operational reliability of the semiconductor apparatus, the plurality of internal clock signals should have a constant phase difference. However, because the plurality of internal clock signals are generated through different clock paths, the phase difference between the plurality of internal clock signals may be changed due to skew of the clock paths. SUMMARY In an embodiment, a duty correction circuit may include a first delay circuit, a second delay circuit, a dividing circuit, a duty detection circuit, and a delay control signal generation circuit. The first delay circuit may be configured to delay a clock signal to generate a first delayed clock signal. The second delay circuit may be configured to variably delay the clock signal based on a delay control signal to generate a second delayed clock signal. The dividing circuit may be configured to divide the first delayed clock signal to generate a first phase clock signal and a third phase clock signal, and may be configured to divide the second delayed clock signal to generate a second phase clock signal and a fourth phase clock signal. The duty detection circuit may be configured to gate the first to fourth phase clock signals to generate a plurality of gating clock signals, and may be configured to generate a duty detection signal based on the plurality of gating clock signals. The delay control signal generation circuit may be configured to generate the delay control signal based on the duty detection signal. In an embodiment, a clock generation circuit may include a phase delay circuit, a first delay circuit, a second delay circuit, a dividing circuit, a clock gating circuit, a duty detector, and a delay control signal generation circuit. The phase delay circuit may be configured to delay a reference clock signal to generate a delay-locked clock signal. The first delay circuit may be configured to delay the delay-locked clock signal to generate a first delayed clock signal. The second delay circuit may be configured to variably delay the delay-locked clock signal to generate a second delayed clock signal based on a delay control signal. The dividing circuit may be configured to divide the first delayed clock signal to generate a first phase clock signal and a third phase clock signal, and may be configured to divide the second delayed clock signal to generate a second phase clock signal and a fourth phase clock signal. The clock gating circuit may be configured to gate the first to fourth phase clock signals to generate a first gating clock signal, a second gating clock signal, a third gating clock signal, a fourth gating clock signal, a fifth gating clock signal, a sixth gating clock signal, a seventh gating clock signal, and an eighth gating clock signal. The duty detector may be configured to generate a first output signal and a second output signal based on the first to eighth gating clock signals, and configured to compare the first and second output signals to generate a duty detection signal. The delay control signal generation circuit may be configured to generate the delay control signal based on the duty detection signal. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration of a clock generation circuit according to an embodiment. FIG. 2 is a