US-12625534-B1 - Processor power control

Abstract

Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases a maximum operating voltage (Vmax) of one or more processors to be dynamically adjusted, based at least in part, on one or more indications of processor usage.

Inventors

• Benjamin D. Faulkner
• Padmanabhan Kannan
• Srinivasan Raghuraman
• Peng Cheng Shen
• Swanand Santosh Bindoo
• Divya Ramakrishnan
• Sreedhar Narayanaswamy
• Amey Y Marathe
• Tanner Malkoff

Assignees

• NVIDIA CORPORATION

Dates

Publication Date

20260512

Application Date

20220422

Claims (14)

1. 1 . One or more processors, comprising circuitry configured to: monitor a first time period during which a voltage of one or more integrated circuits is operating below a threshold operating voltage; identify one or more rates at which credits accrue during the first time period according to one or more types of operations performed by the one or more integrated circuits; accrue credits at the one or more identified rates; and cause a maximum operating voltage (Vmax) of the one or more integrated circuits that is not to be exceeded to be dynamically exceeded based at least on using one or more of the accrued credits.
2. 2 . The one or more processors of claim 1 , wherein the Vmax is to be exceeded based at least on an amount of time the one or more integrated circuits are substantially operated at Vmax.
3. 3 . The one or more processors of claim 1 , wherein the Vmax is to be exceeded based at least on one or more credits associated with an amount of time the one or more integrated circuits are substantially operated at Vmax.
4. 4 . The one or more processors of claim 1 , wherein the Vmax is to be exceeded based, at least in part on one or more indications of operating voltage of one or more of the integrated circuits.
5. 5 . The one or more processors of claim 1 , wherein the Vmax is to be exceeded based at least on the voltage of one or more of the integrated circuits being within a threshold range below the Vmax.
6. 6 . The one or more processors of claim 1 , wherein the accrual of credits is based at least on storing the one or more accrued credits in memory.
7. 7 . A computer-implemented method, comprising: monitoring a first time period during which a voltage of one or more integrated circuits is operating below a threshold operating voltage; identifying one or more rates at which credits accrue during the first time period according to one or more types of operations performed by the one or more integrated circuits; accruing credits at the one or more identified rates; and causing a maximum operating voltage (Vmax) of the one or more integrated circuits that is not to be exceeded to be dynamically exceeded based at least on using one or more of the accrued credits.
8. 8 . The method of claim 7 , wherein the Vmax is to be exceeded based at least on an amount of time the one or more integrated circuits are operated below Vmax.
9. 9 . The method of claim 7 , wherein the Vmax is to be exceeded based at least on one or more credits associated with an amount of time the one or more integrated circuits are operated below Vmax.
10. 10 . A system comprising one or more processors configured to: monitor a first time period during which a voltage of one or more integrated circuits is operating below a threshold operating voltage; identify one or more rates at which credits accrue during the first time period according to one or more types of operations performed by the one or more integrated circuits; accrue credits at the one or more identified rates; and cause a maximum operating voltage (Vmax) of the one or more integrated circuits that is not to be exceeded to be dynamically exceeded based at least on using one or more of the accrued credits.
11. 11 . The system of claim 10 , wherein: the Vmax is to be exceeded based at least on one or more credits associated with increasing Vmax; and the credits are to be accrued while the voltage of the one or more integrated circuits is below Vmax.
12. 12 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to: monitor a first time period during which a voltage of one or more integrated circuits is operating below a threshold operating voltage; identify one or more rates at which credits accrue during the first time period according to one or more types of operations performed by the one or more integrated circuits; accrue credits at the one or more identified rates; and cause a maximum operating voltage (Vmax) of the one or more integrated circuits that is not to be exceeded to be dynamically exceeded based at least on using one or more of the accrued credits.
13. 13 . The non-transitory machine-readable medium of claim 12 , wherein the Vmax is to be exceeded based at least on spending one or more credits associated with increasing the voltage of the one or more integrated circuits until an amount of time elapses.
14. 14 . The non-transitory machine-readable medium of claim 12 , wherein the identification of the one or more rates is further based at least on a data structure that correlates credit accrual with the voltage of the one or more integrated circuits.

Description

FIELD At least one embodiment pertains to processing resources used to execute one or more programs. For example, at least one embodiment pertains to processors or computing systems used cause a device that has been performing under a limit to perform over that limit. BACKGROUND Processors are generally configured to operate without exceeding a maximum operating voltage (Vmax) so they can reliably operate for a number of years. Often, Vmax is set assuming an application will cause a processor's operating voltage to be at or near Vmax for said application's entire runtime. However, an application often does not cause the processor to continuously run at Vmax—there can be periods when the processor is operating at less than Vmax or periods when it is not operating at all. Therefore, setting Vmax statically can be over conservative, which can prevent applications from executing more quickly. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram representing relationships between a controller and processors within a data center to optimize processor performance, according to at least one embodiment; FIG. 2 illustrates a block diagram representing relationships between a controller and processor instances to optimize processor instance performance, according to at least one embodiment; FIG. 3A illustrates a plot of processor utilization used to represent data included in optimizing processor performance, according to at least one embodiment; FIG. 3B illustrates a table representing how credits are used to optimize processor performance, according to at least one embodiment; FIG. 4 illustrates a table representing how credits are used to optimize processor performance, according to at least one embodiment; FIG. 5 illustrates a process for using credits to optimize processor performance, according to at least one embodiment; FIG. 6 illustrates a process for using credits to optimize processor performance, according to at least one embodiment; FIG. 7 illustrates a distributed system, in accordance with at least one embodiment; FIG. 8 illustrates an exemplary data center, in accordance with at least one embodiment; FIG. 9 illustrates a client-server network, in accordance with at least one embodiment; FIG. 10 illustrates an example of a computer network, in accordance with at least one embodiment; FIG. 11A illustrates a networked computer system, in accordance with at least one embodiment; FIG. 11B illustrates a networked computer system, in accordance with at least one embodiment; FIG. 11C illustrates a networked computer system, in accordance with at least one embodiment; FIG. 12 illustrates one or more components of a system environment in which services may be offered as third party network services, in accordance with at least one embodiment; FIG. 13 illustrates a cloud computing environment, in accordance with at least one embodiment; FIG. 14 illustrates a set of functional abstraction layers provided by a cloud computing environment, in accordance with at least one embodiment; FIG. 15 illustrates a supercomputer at a chip level, in accordance with at least one embodiment; FIG. 16 illustrates a supercomputer at a rack module level, in accordance with at least one embodiment; FIG. 17 illustrates a supercomputer at a rack level, in accordance with at least one embodiment; FIG. 18 illustrates a supercomputer at a whole system level, in accordance with at least one embodiment; FIG. 19A illustrates inference and/or training logic, in accordance with at least one embodiment; FIG. 19B illustrates inference and/or training logic, in accordance with at least one embodiment; FIG. 20 illustrates training and deployment of a neural network, in accordance with at least one embodiment; FIG. 21 illustrates an architecture of a system of a network, in accordance with at least one embodiment; FIG. 22 illustrates an architecture of a system of a network, in accordance with at least one embodiment; FIG. 23 illustrates a control plane protocol stack, in accordance with at least one embodiment; FIG. 24 illustrates a user plane protocol stack, in accordance with at least one embodiment; FIG. 25 illustrates components of a core network, in accordance with at least one embodiment; FIG. 26 illustrates components of a system to support network function virtualization (NFV), in accordance with at least one embodiment; FIG. 27 illustrates a processing system, in accordance with at least one embodiment; FIG. 28 illustrates a computer system, in accordance with at least one embodiment; FIG. 29 illustrates a system, in accordance with at least one embodiment; FIG. 30 illustrates an exemplary integrated circuit, in accordance with at least one embodiment; FIG. 31 illustrates a computing system, according to at least one embodiment; FIG. 32 illustrates an APU, in accordance with at least one embodiment; FIG. 33 illustrates a CPU, in accordance with at least one embodiment; FIG. 34 illustrates an exemplary accelerator integratio