US-12625539-B2 - Method and system for controlling a memory device

Abstract

A method of controlling a memory device in which the memory device has a normal mode in which the memory device is operable, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode. The method includes determining a metric based on the time spent by the memory device in at least one previous inactive period. The method further includes comparing the metric with a threshold. Further the method includes in response to determining that the metric is lower than the threshold causing the memory device to remain in the normal mode throughout a subsequent inactive period.

Inventors

• Zhi Gao
• Suneel Varma Uppalapati Venkata

Assignees

• IMAGINATION TECHNOLOGIES LIMITED

Dates

Publication Date

20260512

Application Date

20230310

Priority Date

20220310

Claims (20)

1. 1 . A method of controlling a memory device, the memory device having a normal mode in which the memory device is operable to perform operations including having data read from it and having data written to it, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode, the method comprising: determining a metric based on the time spent by the memory device in at least one previous inactive period; comparing the metric with a threshold; and in response to determining that the metric is lower than the threshold, causing the memory device to remain in the normal mode throughout a subsequent inactive period.
2. 2 . The method according to claim 1 , wherein causing the memory device to remain in the normal mode throughout a subsequent inactive period comprises causing the power save mode to be disabled, so that the memory device cannot be placed in the power save mode and instead remains in the normal mode in the subsequent inactive period.
3. 3 . The method according to claim 1 , further comprising in response to determining that the metric is greater than the threshold causing the memory device to enter the power save mode throughout the subsequent inactive period.
4. 4 . The method according to claim 1 , wherein the threshold is stored in a storage unit, and the threshold is predetermined or programmable.
5. 5 . The method according to claim 1 , further comprising tracking a measure of the time spent during the at least one previous inactive period.
6. 6 . The method according to claim 5 , wherein the measure of the time spent during the at least one previous inactive period is a count of the number of clock cycles spent in the at least one previous inactive period.
7. 7 . The method according to claim 5 , wherein a tracking depth is stored indicating how many previous inactive periods are to be tracked to determine the metric.
8. 8 . The method according to claim 5 , wherein the metric is based on the time spent by the memory device in a plurality of previous inactive periods and determining the metric comprises at least one of: a sum of the measures of the time spent in the previous inactive periods; a weighted sum of the measures of the time spent in the previous inactive periods; an exponential sum of the measures of the time spent in the previous inactive periods; a mean of the measures of the time spent in the previous inactive periods; a median of the measures of the time spent in the previous inactive periods; a mode of the measures of the time spent in the previous inactive periods; a maximum of the measures of the time spent in the previous inactive periods; a minimum of the measures of the time spent in the previous inactive periods; an extrapolated forecast from the measures of the time spent in the previous inactive periods; and a pattern match between the measures of the time spent in the previous inactive periods and a stored plurality of predetermined memory access patterns.
9. 9 . The method according to claim 1 , wherein comparing the metric with the threshold is performed each time the memory device is to enter an inactive state.
10. 10 . A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 1 to be performed when the code is run.
11. 11 . A memory controller for controlling a memory device, the memory device having a normal mode in which the memory device is operable to perform operations including having data read from it and having data written to it, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode, the memory controller comprising: a calculation module configured to determine a metric based on the time spent by the memory device in at least one previous inactive period; a comparator configured to compare the metric with a threshold; and a driver configured to, in response to determining that the metric is lower than the threshold, cause the memory device to remain in the normal mode throughout a subsequent inactive period.
12. 12 . The memory controller according to claim 11 , wherein the driver is configured to, in response to determining that the metric is lower than the threshold, cause the memory device to remain in the normal mode throughout a subsequent inactive period by causing the power save mode to be disabled, so that the memory device cannot be placed in the power save mode and instead remains in the normal mode in the subsequent inactive period.
13. 13 . The memory controller according to claim 11 , wherein the driver is further configured to, in response to determining that the metric is greater than the threshold, cause the memory device to enter the power save mode throughout the subsequent inactive period.
14. 14 . The memory controller according to claim 11 , further comprising a tracking module configured to track a measure of the time duration in the at least one previous inactive period.
15. 15 . The memory controller according to claim 14 , wherein the measure of the time spent during the at least one previous inactive period is a count of the number of clock cycles spent in the at least one previous inactive period.
16. 16 . The memory controller according to claim 14 , wherein the tracking module tracks the time spent by the memory device for a number of inactive periods indicated by a tracking depth stored in a storage module.
17. 17 . The memory controller according to claim 14 , wherein the calculation module determines the metric based on the measure of the time duration in the at least one previous inactive period tracked by the tracking module.
18. 18 . The memory controller according to claim 11 , wherein the memory controller is embodied in fixed function circuitry on an integrated circuit.
19. 19 . A method of manufacturing a memory controller as set forth in claim 11 , comprising inputting a computer readable dataset description of said memory controller into an integrated circuit manufacturing system, and causing said integrated circuit manufacturing system to manufacture said memory controller in accordance with said computer readable dataset description.
20. 20 . A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a memory controller as set forth in claim 11 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the memory controller.

Description

BACKGROUND Memory devices are devices for storing data or information which are to be processed by computing devices. Some memory devices that are directly accessible by processors in the computing devices may be known as main memory or primary memory devices. Such primary memory devices are semiconductor memory blocks or chips that are connected to the processor or integrated with the processor on an SoC. There are also other memory devices such as hard disk, solid state drives (SSD), CD, floppy disk, and the like which may be known as external memory devices (or secondary memory) which are not directly accessible by the computing devices. Examples of primary memory devices include Random Access Memory (RAM), and a permanent storage device called a Read-Only Memory (ROM). The RAM is principally used as a temporary storage by operating systems and applications in the computing device. The operating system and the application read data from and write data into the RAM while performing various functions. Some examples of RAM include dynamic RAM (DRAM), static RAM (SRAM), Synchronous Dynamic RAM (SDRAM), Single Data Rate Synchronous Dynamic RAM (SDR SDRAM), Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) etc. There are also other kinds of primary memory devices such as flash memory and register banks. The primary memory devices of the computing device such as RAM, flash memory and register banks enter into various power modes depending on the operation of the computing device. The different power modes may include a normal mode of operation, a shutdown mode and various power save modes which may be also referred to as self-refresh mode, sleep mode, standby mode, low power mode, ultra-low power mode, etc. The computing devices comprises a memory controller that manages the operation of primary memory devices of the computing device. The memory controller manages the flow of data going to and from the main memory. SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. A first aspect provides a method of controlling a memory device, the memory device having a normal mode in which the memory device is operable and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode. The method comprises determining a metric based on the time spent by the memory device in at least one previous inactive period, comparing the metric with a threshold, and in response to determining that the metric is lower than the threshold causing the memory device to remain in the normal mode throughout a subsequent inactive period. The method may comprise, in response to determining that the metric is lower than the threshold, causing the power save mode to be disabled, so that the memory cannot be placed in the power save mode and instead remains in the normal mode in a subsequent inactive period. A second aspect provides a memory controller for controlling a memory device, the memory device having a normal mode in which the memory device is operable, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode. The memory controller comprises a calculation module configured to determine a metric based on the time spent by the memory device in at least one previous inactive period, a comparator configured to compare the metric with a threshold, and a driver configured to, in response to determining that the metric is lower than the threshold, cause the memory device to remain in the normal mode throughout a subsequent inactive period. The memory controller may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a memory controller. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a memory controller. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a memory controller that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a memory controller. There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of the memory controller; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the memory controller; and an integrated circuit generation