US-12625611-B2 - Metadata registers for a memory device

Abstract

This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

Inventors

• Jungwon Suh
• Pankaj Sharadchandra Deshmukh
• Michael Hawjing Lo
• Subbarao Palacharla
• Olivier Alavoine

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260512

Application Date

20241106

Claims (20)

1. 1 . A DRAM memory, comprising: a DRAM cell memory array comprising a first portion and a second portion; a memory I/O module coupled to the DRAM cell memory array having a plurality of metadata registers, wherein at least one second register of the plurality of metadata registers is configured to associate to a column location of the second portion of the DRAM cell memory array; the memory I/O module further configured to perform operations comprising: receiving data from a host; receiving metadata from the host into the at least one second register of the plurality of metadata registers; storing the data in the first portion of the DRAM cell memory array; and storing the metadata in the column location of the second portion of the DRAM cell memory array.
2. 2 . The DRAM memory of claim 1 , wherein the data and the metadata are received simultaneously during a single write command.
3. 3 . The DRAM memory of claim 1 , wherein the memory I/O module is further configured for performing operations comprising: receiving a first address through at least one non-data connection corresponding to the data, wherein: storing the data in the first portion of the DRAM cell memory array is based on the first address; and storing the metadata in the column location of the second portion of the DRAM cell memory array is to a second address corresponding to the first address.
4. 4 . The DRAM memory of claim 1 , wherein: receiving metadata from the host into the at least one second register comprises receiving a plurality of metadata comprising first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of a page of the DRAM cell memory array; and storing the metadata in the column location of the second portion of the DRAM cell memory array comprises writing the plurality of metadata into the page of the DRAM cell memory array from the at least one second register to complete the first write operation and the second write operation.
5. 5 . The DRAM memory of claim 1 , wherein the metadata comprises an error correction code (ECC).
6. 6 . The DRAM memory of claim 1 , wherein the metadata comprises a signature for authenticating the data corresponding to the metadata.
7. 7 . The DRAM memory of claim 1 , wherein the memory I/O module further comprises a data mask inversion (DMI) portion, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of at least one data connection.
8. 8 . The DRAM memory of claim 1 , wherein the memory I/O module further comprises a read data strobe (RDQS) portion, wherein a number of connections of the read data strobe (RDQS) portion is less than a number of connections of at least one data connection.
9. 9 . The DRAM memory of claim 1 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on a memory address for the data associated with the metadata specified by a write command received by the memory I/O module corresponding to the data.
10. 10 . The DRAM memory of claim 1 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on an indicator specified by a write command received by the memory I/O module.
11. 11 . A method, comprising: receiving data, at a DRAM memory device, into at least one first register; receiving metadata, at the DRAM memory device, into at least one second register of a plurality of metadata registers; storing, by the DRAM memory device, the data from the at least one first register into a first portion of a DRAM cell memory array; and storing, by the DRAM memory device, the metadata from the at least one second register into a column location of a second portion of the DRAM cell memory array, wherein the at least one second register of the plurality of metadata registers is configured to associate to the column location of the second portion of the DRAM cell memory array.
12. 12 . The method of claim 11 , further comprising: retrieving the data from the DRAM cell memory array into the at least one first register; retrieving the metadata from the DRAM cell memory array into the at least one second register; transmitting the data to a host from the at least one first register; and transmitting the metadata to the host from the at least one second register.
13. 13 . The method of claim 11 , further comprising: receiving a first address through at least one non-data connection corresponding to the data, wherein: storing the data in the first portion of the DRAM cell memory array is based on the first address; and storing the metadata in the second portion of the DRAM cell memory array is to a second address corresponding to the first address.
14. 14 . The method of claim 11 , wherein: receiving metadata from a host into the at least one second register comprises receiving a plurality of metadata comprising first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of a page of the DRAM cell memory array; and storing the metadata in the second portion of the DRAM cell memory array comprises writing the plurality of metadata into the page of the DRAM cell memory array from the at least one second register to complete the first write operation and the second write operation.
15. 15 . The method of claim 11 , wherein the metadata comprises an error correction code (ECC).
16. 16 . The method of claim 11 , wherein the metadata comprises a signature for authenticating the data corresponding to the metadata.
17. 17 . The method of claim 11 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on a memory address for the data associated with the metadata specified by a write command corresponding to the data.
18. 18 . The method of claim 11 , wherein storing the metadata comprises storing the metadata into the column location of the second portion based on an indicator specified by a write command.
19. 19 . A method, comprising: retrieving data from a first portion of a DRAM cell memory array into at least one first register; retrieving metadata from a column location of a second portion of the DRAM cell memory array into at least one second register of a plurality of metadata registers, wherein at least one second register of the plurality of metadata registers is configured to associate to the column location of the second portion of the DRAM cell memory array; transmitting the data to a host from the at least one first register; and transmitting the metadata to the host from the at least one second register.
20. 20 . The method of claim 19 , wherein the data and the metadata are retrieved simultaneously during a single read command.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation and claims the benefit of U.S. patent application Ser. No. 18/047,493, entitled, “METADATA REGISTERS FOR A MEMORY DEVICE,” filed on Oct. 18, 2022, which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD Aspects of the present disclosure relate generally to computer information systems, and more particularly, to memory systems for storing data. Some features may enable and provide improved memory capabilities for storing metadata such as error correction codes (ECCs) for data stored in memory. INTRODUCTION A computing device (e.g., a laptop, a mobile phone, etc.) may include one or several processors to perform various computing functions, such as telephony, wireless data access, and camera/video function, etc. A memory is an important component of the computing device. The processors may be coupled to the memory to perform the aforementioned computing functions. For example, the processors may fetch instructions from the memory to perform the computing function and/or to store within the memory temporary data for processing these computing functions, etc. BRIEF SUMMARY OF SOME EXAMPLES The following summarizes some aspects of the present disclosure to provide a basic understanding of the discussed technology. This summary is not an extensive overview of all contemplated features of the disclosure and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in summary form as a prelude to the more detailed description that is presented later. An apparatus in accordance with at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions. In some aspects, registers of a memory device may be configured to separately store data and metadata in different sets of registers. The metadata registers may temporarily store information during transmission between a host device and a memory device for retrieval from a memory array of the memory device in response to a read command or storage in the memory array of the memory device in response to a write command. In one aspect of the disclosure, a memory device includes a memory array comprising a first portion and a second portion; and a memory input/output (I/O) module. The memory I/O module may be coupled to the memory array, configured to communicate with a host through a channel comprising a plurality of connections including at least one data connection and at least one non-data connection, and comprised of at least one first register and at least one second register. The memory I/O module may be configured to perform operations including receiving data from the host via the at least one data connection into the at least one first register; receiving metadata from the host via the at least one non-data connection into the at least one second register; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. The memory I/O module may also be configured to perform operations including retrieving data from the first portion of the memory array into the at least one first register; retrieving metadata from the second portion of the memory array into the at least one second register; transmitting the data to the host via the at least one data connection from the at least one first register; and transmitting the metadata to the host via the at least one non-data connection from the at least one second register. In an additional aspect of the disclosure, an apparatus, such as a wireless device, includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory through a memory controller coupled to a channel that couples the processor to the memory. The processor may be a processor, controller, or other logic circuitry in a host. In an additional aspect of the disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations described herein regarding aspects of the disclosure. The term error-correcting code or codes (ECC or ECCs) in the present disclosure may refer to error detection, error correcting, or error detection and correcting codes. The ECCs are not be limited to a particular type of coding. In some examples, the ECCs may include Hamming codes and/or parity codes. Memories in the present disclosure may be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memories may be of various kinds. For e