US-12625613-B2 - Continuous NAND data-transfer with dynamic TM

Abstract

The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, continuous data-transfer to and from a memory device of the data storage device. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to indirectly delay the transfer without stopping toggling the DQS signals. The toggle mode (TM) speed is dynamically modified slowly during the transfer while considering the current level of the internal write buffer just before writing to the memory device. The transfer can now be accelerated or deaccelerated dynamically during the data transfer. The changes are done slowly so signal integrity issues are avoided.

Inventors

• Shay Benisty
• Yossi Yoseph HASSAN

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260512

Application Date

20221013

Claims (15)

1. 1 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a level of fullness of a write buffer, wherein the determining comprises determining whether the write buffer has exceeded a buffer fullness level threshold of encoded write command data; determine a filling/emptying rate of the write buffer; adjust a toggle mode (TM) speed based upon the determining, wherein adjusting a TM speed comprises changing a pulse width of a data strobe (DQS) signal based on a speed of the filling/emptying rate of the write buffer, wherein the adjusting occurs during data transfer; when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, schedule garbage data writes to the memory device; and write garbage data to the memory device when the write buffer is empty.
2. 2 . The data storage device of claim 1 , wherein the adjusting comprises adjusting the TM speed by an amount of between about 1 percent and about 10 percent.
3. 3 . The data storage device of claim 1 , wherein the adjusting is performed dynamically.
4. 4 . The data storage device of claim 1 , wherein the adjusting comprises gradually changing the TM speed.
5. 5 . The data storage device of claim 1 , wherein the adjusting is performed within a flash interface module (FIM) by a toggle mode adapter coupled to the write buffer.
6. 6 . The data storage device of claim 5 , wherein the FIM also comprises a scheduler.
7. 7 . The data storage device of claim 1 , wherein the write buffer has fullness thresholds.
8. 8 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller includes: a write buffer; a read buffer; and a flash interface module (FIM), wherein: the FIM is coupled to the memory device, the FIM is coupled to the write buffer, the FIM is coupled to the read buffer, the FIM includes a toggle mode (TM) adapter and a scheduler, and the TM adapter is configured to adjust a data strobe signal (DQS) dynamically based upon fullness of either: the write buffer, the read buffer, or both, and upon a speed of a filling/emptying rate of the write buffer, the read buffer, or both, adjusting the DQS dynamically comprises increasing or decreasing a pulse width of the DQS, the adjusting is based upon determining whether the write buffer has exceeded a buffer fullness level threshold of encoded write command data, the TM adapter is configured to dynamically adjust the DQS during data transfer, when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, the controller is configured to schedule garbage data writes to the memory device, when an empty rate of the read buffer is determined to be insufficient to maintain a continuous data transfer, the controller is configured to pause sampling data, and the controller is configured to write garbage data to the memory device when the write buffer is empty.
9. 9 . The data storage device of claim 8 , wherein the adapter is configured to ensure write buffer does not empty by adjusting TM speed.
10. 10 . The data storage device of claim 8 , wherein the adjusting comprises changing the pulse width by a predetermined amount.
11. 11 . The data storage device of claim 10 , wherein two consecutive pulses having different pulse widths.
12. 12 . The data storage device of claim 8 , wherein the controller is configured to transfer data in a read path without sampling the data.
13. 13 . A data storage device, comprising: memory means; and a controller coupled to the memory means, wherein the controller is configured to: determine a filling/emptying rate of a write buffer; dynamically adjust a data strobe signal (DQS) toggle mode (TM) pulse width in response to determining that the write buffer fullness threshold of encoded write command data has been crossed and based on a speed of the filling/emptying rate of the write buffer, wherein the write buffer is distinct from the memory means, wherein the adjusting occurs during data transfer; when a fill rate of the write buffer is determined to be insufficient to maintain a continuous data transfer, schedule garbage data writes to the memory means; and write garbage data to the memory means when the write buffer is empty.
14. 14 . The data storage device of claim 13 , wherein the dynamically adjusting comprises decreasing TM pulse width.
15. 15 . The data storage device of claim 13 , wherein when the write buffer is empty, the controller writes garbage data to the memory means.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation-in-part of U.S. patent application Ser. No. 17/492,175, filed Oct. 1, 2021. The aforementioned related patent application is herein incorporated by reference in its entirety. BACKGROUND OF THE DISCLOSURE Field of the Disclosure Embodiments of the present disclosure generally relate to data storage devices, such as solid state drives (SSDs), and, more specifically, continuous data-transfer to and from a memory device of the data storage device. Description of the Related Art Data input or data output may be paused on a NAND interface by placing the data bus in an idle state. The pausing of data input may be completed by pausing DQS (DQS_t/DWS_c) and holding the relevant signal(s) static high or low until the data burst is resumed. The data burst may be paused if the DQS (DQS_t/DQS_c) or RE_n (RE_t/RE_c) is paused such that the current input/output frequency is not maintained for the data burst. WE_n is held high during data input and output burst pause time. A controller of the data storage device could use the DQS signal in order to pause the data-transfer, but such an approach cannot be used in high toggle mode since the approach introduces signal integrity issues. In another approach, the controller may raise the ALE/CLE signals for pausing the transfer and then issue the warm up cycle to start sending the data again, but such an approach increases the overhead due to extra warm up cycles. In yet another approach, the controller incorporates bigger buffers in the read paths and the write paths, and the write buffer acts as a store and forward buffer. The write data is transferred to the NAND only holding the entire data in the buffer. The read data transfer is initiated only after allocating enough buffers that would be able to absorb the entire data. However, latency may be increased and extra system requirements may be needed due to the size of the buffers. Therefore, there is a need the art for an improved data-transfer that is continuous. SUMMARY OF THE DISCLOSURE The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and, more specifically, continuous data-transfer to and from a memory device of the data storage device. A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to indirectly delay the transfer without stopping toggling the DQS signals. The toggle mode (TM) speed is dynamically modified slowly during the transfer while considering the current level of the internal write buffer just before writing to the memory device. The transfer can now be accelerated or deaccelerated dynamically during the data transfer. The changes are done slowly so signal integrity issues are avoided. In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a level of fullness of a write buffer; and adjust a toggle mode (TM) speed based upon the determining. In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller includes: a write buffer; a read buffer; and a flash interface module (FIM), wherein the FIM is coupled to the memory device, wherein the FIM is coupled to the write buffer, wherein the FIM is coupled to the read buffer, wherein includes a toggle mode (TM) adapter and a scheduler, and wherein the TM adapter is configured to adjust a data strobe signal (DQS) dynamically based upon fullness of either: the write buffer, the read buffer, or both. In another embodiment, a data storage device comprises: memory means; and a controller coupled to the memory means, wherein the controller is configured to: dynamically adjust a data strobe signal (DQS) toggle mode (TM) pulse width in response to determining that a write buffer fullness threshold has been crossed, wherein the write buffer is distinct from the memory means. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. FIG. 1 is a schematic block diagram illustrating a storage system in which a data storage device may function as a storage device for a host device, according to certain embodiments. FIG. 2 is an illustration of an example data input cycle timing, according to certain embodiments. FIG. 3 is a schematic block diagram illustrating a storage system for reading data from and writin