US-12625614-B2 - Charge-sensitive DRAM access timing control

US12625614B2US 12625614 B2US12625614 B2US 12625614B2US-12625614-B2

Abstract

DRAM access timing may be controlled based on charge remaining in cells of a DRAM row. DRAM timing and thus latency may be reduced in instances in which repeated row accesses are directed to the same row within an amount of time during which the row cell capacitances remain highly charged. In response to a row precharge, the row address may be stored in a table. Then, in response to a row activation and subsequent read/write access, a first timing parameter may be used in accessing the row when the row is in the table, and a second timing parameter may be used in accessing the row when the row is not in the table. Entries in the table may be periodically invalidated to reflect charge loss.

Inventors

Darshan Kumar Nandanwar
Sanku Mukherjee
Arvind Garg

Assignees

QUALCOMM INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20231211

Claims (14)

1 . A method for controlling dynamic random access memory (DRAM) access timing, comprising: storing, based on row precharging, an address of a precharged row in a location in a table; determining, based on row activating, whether an address of an activated row is in the table; using a first timing parameter and not a second timing parameter to access the activated row in response to a determination the address of the activated row is in the table; using the second timing parameter and not the first timing parameter to access the activated row in response to a determination the address of the activated row is not in the table; and invalidating the address of the precharged row in the table after a time interval, wherein invalidating comprises invalidating each location in the table every C processor cycles, where C is a number corresponding to an amount of time the precharged row remains charged above a threshold.
2 . The method of claim 1 , wherein the first timing parameter is a shorter time interval between a row activation and a row precharge, and the second timing parameter is a longer time interval between the row activation and the row precharge.
3 . The method of claim 1 , wherein the first timing parameter is a shorter time interval between a row activation and a row read/write access, and the second timing parameter is a longer time interval between the row activation and the row read/write access.
4 . The method of claim 1 , wherein invalidating comprises: incrementing an invalidation interval count of an invalidation interval counter on each processor cycle; determining whether the invalidation interval count is equal to C/k, wherein the table consists of k locations; and in response to determining the invalidation interval count is equal to C/k, invalidating the location in the table indicated by an entry count of an entry counter, incrementing the entry counter after invalidating the location in the table, and resetting the invalidation interval count of the invalidation interval counter.
5 . The method of claim 4 , wherein k=128.
6 . A system for controlling dynamic random access memory (DRAM) access timing, comprising: a table having locations configured to store DRAM row addresses; and a DRAM command manager configured to: detect a precharge command directed to a row, and in response to detecting the precharge command store an address of a precharged row in a location in the table; detect an activate command directed to a row, and in response to detecting the activate command determine whether an address of an activated row is in the table; detect a read/write command, and in response to detecting the read/write command, use a first timing parameter and not a second timing parameter to access the activated row when the address of the activated row is in the table, and use the second timing parameter and not the first timing parameter to access the activated row when the address of the activated row is not in the table; and an invalidation controller configured to invalidate the address of the precharged row in the table after a time interval, wherein the invalidation controller is configured to invalidate each location in the table every C processor cycles, where C is a number corresponding to an amount of time the precharged row remains charged above a threshold.
7 . The system of claim 6 , wherein the first timing parameter is a shorter time interval between a row activation and a row precharge, and the second timing parameter is a longer time interval between the row activation and the row precharge.
8 . The system of claim 6 , wherein the first timing parameter is a shorter time interval between a row activation and a row read/write access, and the second timing parameter is a longer time interval between the row activation and the row read/write access.
9 . The system of claim 6 , wherein the invalidation controller comprises: an entry counter; an invalidation counter configured to increment an invalidation interval count on each processor cycle; and invalidation control circuitry configured to compare the invalidation interval count with a value C/k, wherein the table consists of k locations and, when the invalidation interval count is equal to C/k, invalidate the location in the table indicated by an entry count of the entry counter, increment the entry counter after invalidating the location in the table, and reset the invalidation counter.
10 . The system of claim 9 , wherein k=128.
11 . A dynamic random access memory (DRAM) controller, comprising: a DRAM storage array comprising a plurality of rows; a command generator configured to generate DRAM commands including a precharge command, an activate command, and a read/write command; a table having locations configured to store DRAM row addresses; a DRAM command manager configured to detect the DRAM commands generated by the command generator and to: in response to detecting the precharge command, store an address of a precharged row in a location in the table; in response to detecting the activate command, determine whether an address of an activated row is in the table; and in response to detecting the read/write command, use a first timing parameter and not a second timing parameter to access the activated row when the address of the activated row is in the table, and use the second timing parameter and not the first timing parameter to access the activated row when the address of the activated row is not in the table; and the DRAM command manager includes an invalidation controller configured to invalidate the address of the precharged row in the table after a time interval, wherein the invalidation controller is configured to invalidate each location in the table every C processor cycles, where C is a number corresponding to an amount of time the precharged row remains charged above a threshold.
12 . The DRAM controller of claim 11 , wherein the first timing parameter is a shorter time interval between a row activation and a row precharge, and the second timing parameter is a longer time interval between the row activation and the row precharge.
13 . The DRAM controller of claim 11 , wherein the first timing parameter is a shorter time interval between a row activation and a row read/write access, and the second timing parameter is a longer time interval between the row activation and the row read/write access.
14 . The DRAM controller of claim 11 , wherein the invalidation controller comprises: an entry counter; an invalidation counter configured to increment an invalidation count on each processor cycle; and invalidation control circuitry configured to compare the invalidation count with a value C/k, wherein the table consists of k locations and, when the invalidation count is equal to C/k, to invalidate the location in the table indicated by an entry count of the entry counter, to increment the entry counter after invalidating the location in the table, and to reset the invalidation counter.

Description

DESCRIPTION OF THE RELATED ART Dynamic random access memory (DRAM) may be included in a wide variety of computing devices. A DRAM stores a representation of a data bit in the form of a charge on a capacitance. A DRAM has an array, i.e., rows and columns, of cells where each cell includes such a capacitance. Absent any intervention, the charge would tend to gradually leak, resulting in data loss. A refresh operation is an activation of a row that may be performed periodically to re-charge the cell capacitances and thus prevent data loss. A row also may be activated when the row is accessed to write or read data, similarly re-charging the capacitances. The amount of time between a memory controller activating a DRAM row and data being written to or read from the row following that row activation is commonly referred to as DRAM latency. High DRAM latency may be a memory system bottleneck, adversely impacting memory system performance and thus overall computing device performance. It would be desirable to reduce DRAM latency in a memory system. SUMMARY OF THE DISCLOSURE Systems, methods, and other examples for controlling dynamic random access memory (DRAM) access timing are disclosed. An exemplary method for controlling DRAM access timing may include storing, based on row precharging, an address of the precharged row in a location in a table. The method may further include determining, based on row activating, whether an address of the activated row is in the table. The method may yet further include using a first timing parameter to access the activated row when the address of the activated row is in the table, and using a second timing parameter to access the activated row when the address of the activated row is not in the table. An exemplary system for controlling DRAM access timing may include a DRAM command manager and a table having locations configured to store DRAM row addresses. The DRAM command manager may be configured to detect precharge, activate, and read/write commands. In response to detecting a precharge command, the DRAM command manager may be configured to store the address of the precharged row in a location in the table. In response to detecting an activate command, the DRAM command manager may be configured to determine whether the address of the activated row is in the table. Also in response to detecting a read/write command, the DRAM command manager may be configured to use a first timing parameter to access the activated row when the address of the activated row is in the table, and to use a second timing parameter to access the activated row when the address of the activated row is not in the table. An exemplary DRAM controller may include a DRAM storage array. The DRAM controller may also include a command generator configured to generate DRAM commands including precharge commands, activate commands, and read/write commands. The DRAM controller may include a table configured to store DRAM row addresses and a DRAM command manager configured to detect the DRAM commands generated by the command generator. In response to detecting a precharge command, the DRAM command manager may be configured to store an address of the precharged row in a location in the table. In response to detecting an activate command, the DRAM command manager may be configured to determine whether the address of the activated row is in the table. In response to detecting a read/write command, the DRAM command manager may be configured to use a first timing parameter to access the activated row when the address of the activated row is in the table, and to use a second timing parameter to access the activated row when the address of the activated row is not in the table. BRIEF DESCRIPTION OF THE DRAWINGS In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “101A” or “101B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all Figures. FIG. 1 is a block diagram of a portion of a computing system having a feature for controlling DRAM access timing, in accordance with exemplary embodiments. FIG. 2 is a diagram showing the effects on a DRAM cell of commands relating to a read operation over a time interval, in accordance with exemplary embodiments. FIG. 3 is a block diagram of a memory controller, in accordance with exemplary embodiments. FIG. 4 illustrates an exemplary highly-charged row (HCR) table, in accordance with exemplary embodiments. FIG. 5 is a flowchart illustrating a method for controlling DRAM access timing, in accordance with exemplary embodiments. DETAILED DESCRIPTION The word “exemplary” is used herein to mean “serving as an example, instance, or illus