US-12625615-B2 - Boot operations and logical block addresses

US12625615B2US 12625615 B2US12625615 B2US 12625615B2US-12625615-B2

Abstract

Methods, systems, and devices for boot operations and logical block addresses are described. A memory system may identify logical block addresses (LBAs) that are more frequently accessed during the boot phase relative to other LBAs. Such LBAs may be referred to herein as boot LBAs. For example, the memory system may maintain a counter for each LBA read during the boot phase, which may enable the memory system to track and record the frequency of each LBA accessed during the boot phase. Using the information gathered about the boot LBAs (e.g., the quantity of accesses of each boot LBA), the memory system may perform a defragmentation process, which may be triggered by a host system, to consolidate the boot LBAs within a threshold quantity of memory blocks. In some examples, defragmentation of the boot LBAs may also be based on a sequence of the boot LBAs.

Inventors

Marco Redaelli

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20240729

Claims (20)

1 . A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: access a logical block address (LBA) of a plurality of LBAs as part of a boot operation of a plurality of boot operations; increment a counter associated with the LBA based on accessing the LBA, wherein a quantity of accesses of the LBA is based on the counter; receive an indication to perform a defragmentation process of a subset of the plurality of LBAs based on the quantity of accesses performed as part of the plurality of boot operations, wherein the subset of the plurality of LBAs comprises the LBA; and transfer, as part of the defragmentation process, one or more LBAs of the subset from one or more first blocks of the memory system to one or more second blocks of the memory system based on the indication.
2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: determine, over the plurality of boot operations of the memory system, that the quantity of accesses of the LBA satisfies a threshold, wherein receiving the indication is based on the quantity of accesses satisfying the threshold.
3 . The memory system of claim 1 , wherein the one or more second blocks of the memory system comprise the subset of the plurality of LBAs based on the defragmentation process, and wherein the one or more second blocks of the memory system satisfy a threshold quantity of blocks.
4 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: initiate a learning procedure associated with determining, over the plurality of boot operations, which of the plurality of LBAs satisfy a threshold quantity of accesses; and maintain a plurality of counters, including the counter, each counter corresponding to a respective quantity of accesses of a respective LBA of the plurality of LBAs, wherein incrementing the counter is based on maintaining the plurality of counters.
5 . The memory system of claim 4 , wherein the processing circuitry is further configured to cause the memory system to: determine to stop the learning procedure based on a completion of the plurality of boot operations; and perform the defragmentation process based on the determination to stop the learning procedure.
6 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: receive a second indication to reset the counter associated with the LBA; and set the counter to a first value based on receiving the second indication.
7 . The memory system of claim 6 , wherein the processing circuitry is further configured to cause the memory system to: determine, over a second plurality of boot operations of the memory system, a second quantity of accesses of the LBA as part of the second plurality of boot operations based on setting the counter to the first value.
8 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: generate a mapping between a logical address of the LBA and a physical address of the LBA based on transferring the one or more LBAs of the subset; load the mapping as part of the boot operation of the plurality of boot operations; and determine the physical address of the LBA based on the mapping.
9 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: perform a snap read of a set of LBAs comprising the LBA of a first plane of the memory system and one or more other LBAs of one or more other planes of the memory system, wherein a first placement of the LBA in the first plane and a second placement of the one or more other LBAs in the one or more other planes is based on transferring the one or more LBAs of the subset.
10 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: assign a priority to the LBA based on the quantity of accesses of the LBA, a sequential order of the LBA relative to other LBAs of the plurality of LBAs, or both, wherein transferring the one or more LBAs of the subset is based on the priority.
11 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: perform, as part of the boot operation of the plurality of boot operations, a first access of the one or more second blocks comprising the LBA and a second access of a third block that is sequentially-indexed with the one or more second blocks based on transferring the one or more LBAs of the subset.
12 . The memory system of claim 1 , wherein receiving the indication to perform the defragmentation process comprises the processing circuitry configured to cause the memory system to: receive the indication to perform the defragmentation process during an idle period or a charging period of the memory system.
13 . A method by a memory system, comprising: accessing a logical block address (LBA) of a plurality of LBAs as part of a boot operation of a plurality of boot operations; incrementing a counter associated with the LBA based on accessing the LBA, wherein a quantity of accesses of the LBA is based on the counter; receiving an indication to perform a defragmentation process of a subset of the plurality of LBAs based on the quantity of accesses performed as part of the plurality of boot operations, wherein the subset of the plurality of LBAs comprises the LBA; and transferring, as part of the defragmentation process, one or more LBAs of the subset from one or more first blocks of the memory system to one or more second blocks of the memory system based on the indication.
14 . The method of claim 13 , further comprising: determining, over the plurality of boot operations of the memory system, that the quantity of accesses of the LBA satisfies a threshold, wherein receiving the indication is based on the quantity of accesses satisfying the threshold.
15 . The method of claim 13 , further comprising: receiving a second indication to reset the counter associated with the LBA; and setting the counter to a first value based on receiving the second indication.
16 . The method of claim 15 , further comprising: determining, over a second plurality of boot operations of the memory system, a second quantity of accesses of the LBA as part of the second plurality of boot operations based on setting the counter to the first value.
17 . The method of claim 13 , further comprising: generating a mapping between a logical address of the LBA and a physical address of the LBA based on transferring the one or more LBAs of the subset; loading the mapping as part of the boot operation of the plurality of boot operations; and determining the physical address of the LBA based on the mapping.
18 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: access a logical block address (LBA) of a plurality of LBAs as part of a boot operation of a plurality of boot operations; increment a counter associated with the LBA based on accessing the LBA, wherein a quantity of accesses of the LBA is based on the counter; receive an indication to perform a defragmentation process of a subset of the plurality of LBAs based on the quantity of accesses performed as part of the plurality of boot operations, wherein the subset of the plurality of LBAs comprises the LBA; and transfer, as part of the defragmentation process, one or more LBAs of the subset from one or more first blocks to one or more second blocks based on the indication.
19 . The non-transitory computer-readable medium of claim 18 , wherein the instructions are further executable by the one or more processors to: determine, over the plurality of boot operations, that the quantity of accesses of the LBA satisfies a threshold, wherein receiving the indication is based on the quantity of accesses satisfying the threshold.
20 . The non-transitory computer-readable medium of claim 18 wherein the instructions are further executable by the one or more processors to: receive a second indication to reset the counter associated with the LBA; and set the counter to a first value based on receiving the second indication.

Description

CROSS REFERENCE The present Application for Patent claims priority to U.S. Patent Application No. 63/559,485 by Redaelli, entitled “BOOT OPERATIONS AND LOGICAL BLOCK ADDRESSES,” filed Feb. 29, 2024, which is assigned to the assignee hereof, and which is expressly incorporated by reference in its entirety herein. TECHNICAL FIELD The following relates to one or more systems for memory, including boot operations and logical block addresses. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not- or (NOR) and not- and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of a system that supports boot operations and logical block addresses in accordance with examples as disclosed herein. FIG. 2 shows an example of a flow diagram that supports boot operations and logical block addresses in accordance with examples as disclosed herein. FIG. 3 shows an example of an architecture that supports boot operations and logical block addresses in accordance with examples as disclosed herein. FIG. 4 shows a block diagram of a memory system that supports boot operations and logical block addresses in accordance with examples as disclosed herein. FIG. 5 shows a flowchart illustrating a method or methods that support boot operations and logical block addresses in accordance with examples as disclosed herein. DETAILED DESCRIPTION After a memory system (e.g., a solid state drive (SSD) powers on or resets, the memory system may perform a boot phase, or a boot operation, in which the memory system may perform various operations or procedures to achieve a fully operational state. In some examples, the boot phase takes an amount of time (e.g., two minutes) after power on or reset. The memory system may perform read operations of logical block addresses (LBAs) during the boot phase, and, in some cases, one or more sequences (e.g., logical sequences) of LBAs may be read from the system, which may contain boot-related data. However, LBAs that the memory system accesses during boot may be scattered, or fragmented, in memory (e.g., across multiple blocks), which may result in slow boot times and inefficient system startup (e.g., in systems that utilize SSDs). To improve efficiency of system startup and reduce boot times, techniques described herein may provide for the memory system to learn (e.g., identify, store, track, and/or update) LBAs that are more frequently accessed during the boot phase relative to other LBAs (e.g., LBAs that satisfy an access frequency threshold). Such LBAs may be referred to herein as boot LBAs. A boot LBA may be defined as an LBA read within a specific time period when the system is implementing a boot-up procedure. The boot LBA recording time can be user configurable within the available memory footprint. In some examples, the memory system may maintain a counter for each LBA read during the boot phase (or maintain counters for each group of LBAs read during the boot phase), which may enable the memory system to track and record (e.g., store in memory) the frequency of each LBA accessed during the boot phase. Using the information (e.g., quantity of accesses) gathered about the boot LBAs, the memory system may perform a defragmentation process, which may be triggered by a host system, to consolidate the boot LBAs within a threshold quantity of memory blocks. By defragmenting (e.g., consolidating) the boot LBAs, the memory system may enable relatively faster retrieval of the boot LBAs during subsequent boot phases, or cycles. For example, the memory system m