US-12625617-B2 - Data separation configurations for memory systems

US12625617B2US 12625617 B2US12625617 B2US 12625617B2US-12625617-B2

Abstract

Methods, systems, and devices for data separation configurations for memory systems are described. A memory system may store one or more characteristics of data, which may be utilized to improve performance associated with transferring the data between blocks of memory cells. For example, a memory system may be configured to evaluate whether to separate data in one or more transfer operations based on the characteristics of the data. Some transfer configurations may include transferring data independent of characteristics of the data and some other transfer configurations may include transferring data based on characteristics of the data. In some examples, a transfer configuration may include transferring data associated with a relatively longer validity duration characteristic before transferring data associated with a relatively shorter validity duration characteristic, which may include transferring data associated with different validity duration characteristics to the same target block or to different target blocks.

Inventors

Nitul Gohain
Nicola Colella

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20240219

Claims (20)

1 . An apparatus, comprising: one or more memory devices of a memory system; and a controller of the memory system coupled with the one or more memory devices and configured to cause the apparatus to: write data associated with two or more different validity characteristics to a block of memory cells of the one or more memory devices; determine, for a transfer operation to transfer the data associated with the two or more different validity characteristics from the block of memory cells, whether to write the data associated with the two or more different validity characteristics to a same target block of memory cells of the one or more memory devices or to write the data associated with the two or more different validity characteristics to multiple target blocks of memory cells of the one or more memory devices each corresponding to a respective validity characteristic of the two or more different validity characteristics; and perform the transfer operation based at least in part on the determination.
2 . The apparatus of claim 1 , wherein, to perform the transfer operation, the controller is configured to cause the apparatus to: write, based at least in part on determining to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells, a first portion of the data associated with a first validity characteristic of the two or more different validity characteristics to a first target block that corresponds to the first validity characteristic, and a second portion of the data associated with a second validity characteristic of the two or more different validity characteristics to a second target block that corresponds to the second validity characteristic.
3 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on one or more operating conditions of the memory system.
4 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on an amount of available space of a set of one or more blocks of memory cells that includes the block of memory cells.
5 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on an input/output pattern for the memory system.
6 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on a resource availability of the memory system.
7 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on a temperature of the memory system.
8 . The apparatus of claim 1 , wherein the controller is configured to cause the apparatus to: determine whether to write the data associated with the two or more different validity characteristics to the same target block of memory cells or to write the data associated with the two or more different validity characteristics to the multiple target blocks of memory cells based at least in part on a storage density of the block of memory cells, or on a target block storage density, or a combination thereof.
9 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: determine a target block storage density for the transfer operation based at least in part on one or more operating conditions of the memory system.
10 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: select the block of memory cells for the transfer operation based at least in part on an amount of the data that is associated with a validity characteristic of the two or more different validity characteristics.
11 . The apparatus of claim 10 , wherein the controller is further configured to cause the apparatus to: determine the amount of the data that is associated with the validity characteristic based at least in part on reading a data quantity indicator for the validity characteristic that corresponds to the block of memory cells.
12 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: select the block of memory cells for the transfer operation based at least in part on a duration that the data has been stored in the block of memory cells.
13 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: select the block of memory cells for the transfer operation based at least in part on a quantity of erase cycles associated with the block of memory cells.
14 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: write indications of the two or more different validity characteristics associated with respective portions of the data to a logical-to-physical address mapping table associated with the block of memory cells.
15 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: update a validity characteristic associated with at least a portion of the data based at least in part on a duration of validity of the at least the portion of the data at the memory system.
16 . The apparatus of claim 1 , wherein each validity characteristic of the two or more different validity characteristics is associated with a respective data validity duration, or with a respective data type.
17 . The apparatus of claim 1 , wherein each validity characteristic of the two or more different validity characteristics is associated with a respective stream identifier.
18 . An apparatus, comprising: one or more memory devices of a memory system; and a controller of the memory system coupled with the one or more memory devices and configured to cause the apparatus to: write data associated with two or more different validity characteristics to a block of memory cells of the one or more memory devices; determine, for a transfer operation, whether to transfer the data associated with the two or more different validity characteristics or to transfer a portion of the data associated with fewer than all of the two or more different validity characteristics; and perform the transfer operation based at least in part on the determination.
19 . The apparatus of claim 18 , wherein, to perform the transfer operation, the controller is configured to cause the apparatus to: invalidate the portion of the data in the block of memory cells, based at least in part on determining to transfer the portion of the data, after transferring the portion of the data to a second block of memory cells of the one or more memory devices; and maintain a validity of a second portion of the data, associated with at least one validity characteristic of the two or more different validity characteristics, in the block of memory cells.
20 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: write data associated with two or more different validity characteristics to a block of memory cells of the electronic device; determine, for a transfer operation to transfer the data associated with the two or more different validity characteristics from the block of memory cells, whether to write the data associated with the two or more different validity characteristics to a same target block of memory cells of the electronic device or to write the data associated with the two or more different validity characteristics to multiple target blocks of memory cells of the electronic device each corresponding to a respective validity characteristic of the two or more different validity characteristics; and perform the transfer operation based at least in part on the determination.

Description

CROSS REFERENCE The present Application for Patent claims the benefit of U.S. Provisional Patent Application No. 63/447,778 by GOHAIN et al., entitled “DATA SEPARATION CONFIGURATIONS FOR MEMORY SYSTEMS,” filed Feb. 23, 2023, assigned to the assignee hereof, and expressly incorporated by reference in its entirety herein. TECHNICAL FIELD The following relates to one or more systems for memory, including data separation configurations for memory systems. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states if disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system that supports data separation configurations for memory systems in accordance with examples as disclosed herein. FIG. 2 illustrates an example of a data transfer operation that supports data separation configurations for memory systems in accordance with examples as disclosed herein. FIG. 3 illustrates an example of a data transfer operation that supports data separation configurations for memory systems in accordance with examples as disclosed herein. FIG. 4 illustrates a block diagram of a memory system that supports data separation configurations for memory systems in accordance with examples as disclosed herein. FIGS. 5 and 6 illustrate flowcharts showing methods that support data separation configurations for memory systems in accordance with examples as disclosed herein. DETAILED DESCRIPTION Memory systems may store data with different characteristics, such as data of different types, data associated with different validity characteristics (e.g., different validity durations), or data associated with different stream identifiers. For example, a memory system may store data associated with an operating system or an application, which may be valid (e.g., maintained) for a relatively long duration, and may store streaming data or other transient data, which may be valid for a relatively short duration (e.g., may be eligible for erasure after a relatively short duration). In some implementations, data may be associated with a ‘temperature’ indication, where data that is expected to be valid for relatively longer durations may be referred to as cold data, and data that is expected to be valid for relatively shorter durations may be referred to as hot data. In some cases, a memory system may transfer data between blocks of memory cells (e.g., as part of a media management operation). For example, a memory system may transfer data as part of a folding operation (e.g., a flush operation, to transfer data from relatively a relatively low-density block of memory cells to a relatively high-density block of memory cells), as part of a garbage collection operation (e.g., to make a block of memory cells available for erasure), or as part of a wear-leveling operation (e.g., to support a more-uniform accumulation of wear across blocks of memory cells), among other transfer operations. However, some memory systems may not differentiate data or differentiate management of data based on respective data characteristics (e.g., data temperatures), which may result in various inefficiencies. For example, media management operations that do not account for data characteristics may result in resources being allocated for the transfer of relatively hot data, which may cause undue processing allocation, power allocation, or wear on memory cells due to the relatively temporary nature of relatively hot data that may be invalidated relatively quickly. In accordance with examples as disclose