US-12625622-B2 - Selectively disabling memory devices

Abstract

In some implementations, a memory device may obtain, via a channel coupled to one or more memory devices of a memory system, one or more signals indicating respective power consumptions of the one or more memory devices, wherein the memory device is included in the one or more memory devices. The memory device may identify an interruption associated with the one or more signals. The memory device may determine, based on the identification of the interruption, whether a host system associated with the memory system is authorized to access the memory device. The memory device may selectively, based on the determination of whether the host system is authorized to access the memory device, perform a disablement operation on the memory device or perform one or more second commands obtained from the host system.

Inventors

• Yu-Chung Lien
• Tomer Tzvi Eliash
• Zhenming Zhou

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240730

Claims (20)

1. 1 . A memory device, comprising: one or more components configured to: obtain, via a channel coupled to one or more memory devices of a memory system, one or more signals indicating respective power consumptions of the one or more memory devices, wherein the memory device is included in the one or more memory devices; identify an interruption associated with the one or more signals; determine, based on the identification of the interruption, whether a host system associated with the memory system is authorized to access the memory device; and selectively, based on the determination of whether the host system is authorized to access the memory device, perform a disablement operation on the memory device or perform one or more second commands obtained from the host system.
2. 2 . The memory device of claim 1 , wherein, to selectively perform the disablement operation or perform the one or more second commands, the one or more components are configured to: determine, using a security module of the memory device, that the host system is not authorized to access the memory device; and perform, based on the determination that the host system is not authorized to access the memory device, the disablement operation.
3. 3 . The memory device of claim 2 , wherein the one or more components are further configured to: obtain, from the host system, the one or more second commands; and refrain, based on the determination that the host system is not authorized to access the memory device, from performing the one or more second commands.
4. 4 . The memory device of claim 2 , wherein, to determine that the host system is not authorized to access the memory device, the one or more components are configured to: provide, to the host system, a message, the message based on one or more cryptographic keys associated with the security module; obtain, from the host system, a response to the message; and determine, based on the response and based on the one or more cryptographic keys, that the host system is not authorized to access the memory device.
5. 5 . The memory device of claim 2 , wherein the security module is a hardware root of trust.
6. 6 . The memory device of claim 1 , wherein, to selectively perform the disablement operation or perform the one or more second commands, the one or more components are configured to: determine, using a security module of the memory device, that the host system is authorized to access the memory device; perform, based on the determination that the host system is authorized to access the memory device, the one or more second commands; and refrain, based on the determination that the host system is authorized to access the memory device, from performing the disablement operation.
7. 7 . The memory device of claim 1 , wherein the one or more components are configured to obtain the one or more signals during a first duration, and wherein, to identify the interruption, the one or more components are configured to: identify that a second one or more signals are not obtained, the second one or more signals indicating second respective power consumptions of the one or more memory devices during a second duration, wherein the second duration is after the first duration.
8. 8 . The memory device of claim 1 , wherein the disablement operation comprises reducing a supply voltage of the memory device such that the supply voltage does not satisfy an operation threshold of the memory device.
9. 9 . The memory device of claim 1 , wherein the disablement operation comprises erasing metadata associated with accessing the memory device.
10. 10 . The memory device of claim 9 , wherein the metadata is stored to at least one of one or more fuses of the memory device or one or more antifuses of the memory device.
11. 11 . The memory device of claim 1 , wherein the disablement operation comprises applying a voltage to a communication circuit coupled to the memory device and coupled to a controller associated with the memory device, wherein the voltage exceeds an operating range of the communication circuit.
12. 12 . The memory device of claim 11 , wherein the communication circuit is an open not-and (NAND) flash interface (ONFI) channel.
13. 13 . The memory device of claim 1 , wherein the disablement operation comprises applying a voltage to a timing circuit of the memory device, wherein the voltage exceeds an operating range of the timing circuit.
14. 14 . The memory device of claim 13 , wherein the timing circuit is an oscillator associated with a clock signal of the memory device.
15. 15 . A memory device, comprising: one or more components configured to: obtain, via a channel coupled to one or more memory devices of a memory system, a clock signal associated with the one or more memory devices, wherein the memory device is included in the one or more memory devices; identify an interruption associated with the clock signal; determine, based on the identification of the interruption, whether a host system associated with the memory system is authorized to access the memory device; and selectively, based on the determination of whether the host system is authorized to access the memory device, perform a disablement operation on the memory device or perform one or more second commands obtained from the host system.
16. 16 . The memory device of claim 15 , wherein the one or more components are configured to obtain the clock signal during a first duration, and wherein, to identify the interruption, the one or more components are configured to: identify that the clock signal is not received during a second duration after the first duration.
17. 17 . The memory device of claim 15 , wherein, to selectively perform the disablement operation or perform the one or more second commands, the one or more components are configured to: determine, using a security module of the memory device, that the host system is not authorized to access the memory device; and perform, based on the determination that the host system is not authorized to access the memory device, the disablement operation.
18. 18 . The memory device of claim 15 , wherein, to selectively perform the disablement operation or perform the one or more second commands, the one or more components are configured to: determine, using a security module of the memory device, that the host system is authorized to access the memory device; perform, based on the determination that the host system is authorized to access the memory device, the one or more second commands; and refrain, based on the determination that the host system is authorized to access the memory device, from performing the disablement operation.
19. 19 . A memory device, comprising: one or more components configured to: obtain, via a channel coupled to one or more memory devices of a memory system, one or more signals associated with the one or more memory devices, wherein the memory device is included in the one or more memory devices; identify an interruption associated with the one or more signals; provide, to a host system associated with the memory system, a message, the message based on one or more cryptographic keys associated with a security module of the memory device; obtain, from the host system, a response to the message; determine, based on the response and based on the one or more cryptographic keys, whether the host system is authorized to access the memory device; and selectively, based on the determination of whether the host system is authorized to access the memory device, perform a disablement operation on the memory device or perform one or more second commands obtained from the host system.
20. 20 . The memory device of claim 19 , wherein, to selectively perform the disablement operation or perform the one or more second commands, the one or more components are configured to: perform, based on a determination that the host system is not authorized to access the memory device, the disablement operation.

Description

TECHNICAL FIELD The present disclosure generally relates to memory devices, memory device operations, and, for example, to selectively disabling memory devices. BACKGROUND Memory devices are widely used to store information in various electronic devices. A memory device includes memory cells. A memory cell is an electronic circuit capable of being programmed to a data state of two or more data states. For example, a memory cell may be programmed to a data state that represents a single binary value, often denoted by a binary “1” or a binary “0.” As another example, a memory cell may be programmed to a data state that represents a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device may write to, or program, a set of memory cells. To access the stored information, the electronic device may read, or sense, the stored state from the set of memory cells. Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and others. A memory device may be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for extended periods of time even in the absence of an external power source. Volatile memory (e.g., DRAM) may lose stored data over time unless the volatile memory is refreshed by a power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an example system capable of selectively disabling memory devices. FIG. 2 is a diagram illustrating a system that supports selectively disabling memory devices. FIG. 3 is a diagram of a process that supports selectively disabling memory devices. FIG. 4 is a flowchart of an example method associated with selectively disabling memory devices. FIG. 5 is a flowchart of an example method associated with selectively disabling memory devices. FIG. 6 is a flowchart of an example method associated with selectively disabling memory devices. DETAILED DESCRIPTION Products of a memory system manufacturer may be subject to unauthorized attempts from third parties to access internal aspects of a memory system. For example, as memory technology improves, unauthorized third parties, such as a competitor memory system manufacturer, may attempt to probe a memory system to observe internal signaling, such as signaling between memory devices of the memory system. Such internal signaling may reveal sensitive or otherwise classified information of the memory system, such as timing information of the memory device, operational modes supported by the memory device, and/or signaling characteristics (e.g., voltage levels and/or waveforms of signaling associated with the memory device), among other examples. To achieve such probing, an unauthorized third party may attempt to remove a memory device from the memory system during operation of the memory system. For example, the unauthorized third party may attempt to physically remove the memory device and couple the memory device to an unauthorized host system or otherwise reroute signaling from the memory device to an unauthorized host system. The unauthorized host system may then control the memory device by imitating a legitimate host system and/or controller of the memory system (e.g., the unauthorized host system may attempt to “spoof” the memory device). For example, the unauthorized host system may issue one or more commands to the memory device. By responding to such commands, the memory device may reveal sensitive information to the unauthorized host system, which may pose a security risk to the memory system and other products of the memory system manufacturer (e.g., by revealing aspects of security protocols implemented by the memory system). Some implementations as described herein enable selectively disabling memory devices. For example, a memory system may include one or more memory devices that may communicate via a shared channel (e.g., using cross-die communication, as described in greater detail elsewhere herein). A memory device may monitor one or more signals obtained from other memory device(s) of the memory system via the shared channel, such as one or more power management signals obtained from each of the other memory device(s) and/or a clock signal obtained from (one of) the other memory device(s). If the memory device identifies an interruption in the one or more signals, the memory device may determine that an unauthorized host system may be attempting to access the memory device. The memory device may determine whether the host system is authorized to access the memory device. For example, the memory device may provide, and the host system may obtain, an authentication message requesting to verify the identity of the host system. The memory device may include a security module that stores one