US-12625624-B2 - Systems, methods, and devices for power domain management

US12625624B2US 12625624 B2US12625624 B2US 12625624B2US-12625624-B2

Abstract

Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.

Inventors

Itzic Cohen
Yair Sofer
Guy Levi
Eran Geyari

Assignees

Infineon Technologies LLC

Dates

Publication Date: 20260512
Application Date: 20231214

Claims (14)

1 . A method comprising: activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, wherein the memory command includes a read command; performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain, wherein the first portion identifies a read operation; activating a second power domain of the memory controller based on a timing determined based on the sequence of operations; and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain, wherein the second portion identifies a data verification operation and wherein the activating of the second power domain is performed parallel to the read operation.
2 . The method of claim 1 , wherein the read command identifying data to be read from the storage location.
3 . The method of claim 1 , wherein the data verification operation comprises: Computing an error correction code (ECC) based on the data read from the storage location.
4 . The method of claim 1 , wherein the activating of the first power domain and the activating of the second power domain further comprise: transitioning from a depowered state to a powered state.
5 . The method of claim 1 , wherein associations between the sequence of operations and power domains are stored by the memory controller in a designated mapping.
6 . The method of claim 1 further comprising: determining timing information for the activation of the second power domain based, at least in part, on data representing the sequence of operations.
7 . The method of claim 1 further comprising: receiving an additional memory command; activating a third power domain of the memory controller; and performing at least some of the additional memory command using a third plurality of processing elements included in the third power domain.
8 . A system comprising: a nonvolatile memory array; and a memory controller configured to: activate a first power domain in response to receiving a memory command associated with the nonvolatile memory array; perform a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain; activate a second power domain based on a timing determined based on the sequence of operations; and perform a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain, wherein the first portion identifies a read operation, wherein the second portion identifies a data verification operation, and wherein the activating of the second power domain is performed parallel to the read operation.
9 . The system of claim 8 further comprising: a first power supply coupled to the first power domain and configured to activate the first power domain in response to a first control signal received from the memory controller; and a second power supply coupled to the second power domain and configured to activate the second power domain in response to a second control signal received from the memory controller.
10 . The system of claim 8 , wherein the data verification operation comprises computing an error correction code (ECC) based on the data read from the nonvolatile memory array.
11 . The system of claim 8 , wherein associations between the sequence of operations and power domains are stored by the memory controller in a designated mapping.
12 . A device comprising: a memory controller configured to: activate a first power domain in response to receiving a memory command associated with a nonvolatile memory array; perform a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain; activate a second power domain based on a timing determined based on the sequence of operations; and perform a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain, wherein the first portion identifies a read operation, and wherein the second portion identifies a data verification operation, and wherein the activating of the second power domain is performed parallel to the read operation.
13 . The device of claim 12 , wherein the nonvolatile memory array is a resistive random access memory (RRAM) array.
14 . The device of claim 12 , wherein the data verification operation comprises computing an error correction code (ECC) based on the data read from the nonvolatile memory array.

Description

TECHNICAL FIELD This disclosure relates to management of power domains, and more specifically, to enhancement of management of power domains associated with memory. BACKGROUND Memory modules may include components, such as a memory controller and a memory array. The memory controller may receive commands from other components and process those commands to execute read and write operations associated with the memory array. Accordingly, the memory controller may include processing logic configured to perform such read and write operations. Conventional techniques for implementing such memory controllers remain limited because they remain inefficient in power consumption associated with usage of such processing logic. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system for power domain management, configured in accordance with some embodiments. FIG. 2 illustrates an example of a device for power domain management, configured in accordance with some embodiments. FIG. 3 illustrates another example of a device for power domain management, configured in accordance with some embodiments. FIG. 4 illustrates an additional example of a device for power domain management, configured in accordance with some embodiments. FIG. 5 illustrates an image of a timing diagram of commands and operations associated with power domain management, performed in accordance with some embodiments. FIG. 6 illustrates a flow chart of an example of a method for power domain management, performed in accordance with some embodiments. FIG. 7 illustrates a flow chart of another example of a method for power domain management, performed in accordance with some embodiments. DETAILED DESCRIPTION In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented concepts. The presented concepts may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as not to unnecessarily obscure the described concepts. While some concepts will be described in conjunction with the specific examples, it will be understood that these examples are not intended to be limiting. Memory controllers may include processing logic configured to execute various operations associated with memory accesses. Accordingly, different portions of such processing logic may be configured to perform different operations associated with a particular memory command. For example, a read command may be issued to request data to be read from memory. Such a read command may include multiple different memory operations, such as a read operation and a data verification operation. In various embodiments, such operations may be performed serially as the data is read out of the memory array before it is verified by the memory controller. Conventional techniques for implementing such memory commands remain limited because processing logic for different operations remains powered, even when not in use, thus resulting in inefficient power consumption by the memory controller and relatively high leakage currents from unused processing logic that remains powered. Embodiments disclosed herein provide dynamic implementation and activation of different power domains for different portions of memory operations. As will be discussed in greater detail below, different power domains may correspond to different operations associated with a memory command, and such power domains may be activated dynamically depending on their usage within the context of execution of the memory command. Accordingly, as will be discussed in greater detail below, power domains are used dynamically as they are invoked, and an overall power consumption of the memory controller executing the memory command is reduced. Moreover, a leakage current is also reduced, where such a leakage current may be associated with processing elements that remain powered even during a standby mode. FIG. 1 illustrates an example of a system for power domain management, configured in accordance with some embodiments. As similarly discussed above, a system, such as system 100, may include and manage multiple power domains to stagger their activation when reading data from memory. As will be discussed in greater detail below, increased granularity in power domain control and activation during memory operations improves the efficiency of usage of such power domains as well as power consumption incurred by such power domain usage and an associated leakage current. As shown in FIG. 1, system 100 includes host processor 108 which is configured to perform one or more processing operations that may be associated with a host application or other user application. In one example, host processor 108 may be a microcontroller configured to execute commands that may include user-defined commands. Accordingly, commands may be generated by host processor 108 and may be passed to another co