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US-12625625-B2 - Reduced power addressing

US12625625B2US 12625625 B2US12625625 B2US 12625625B2US-12625625-B2

Abstract

An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.

Inventors

  • Leon Zlotnik
  • Leonid Minz

Assignees

  • MICRON TECHNOLOGY, INC.

Dates

Publication Date
20260512
Application Date
20240710

Claims (20)

  1. 1 . A method, comprising: selectively transferring, from a first selection component and responsive to receiving a first access request and a second access request respectively to access a first target component, a number of address bits of the first access request or the second access request to a first address encoder; converting, at the first address encoder, a format of the number of address bits from a first format to a second format, wherein the second format corresponds to a reduced Hamming distance binary code format that involves a reduced number of toggles in accessing the first target component than using the first format; accessing the first target component using the number of address bits having the second format; receiving a third access request with address bits having the first format to access a second target component, wherein the second target component is not compatible with access via address bits having the second format; and transferring, to the second target component, the third access request with the address bits having the first format as is to cause the third access request to be executed at the target component with the address bits in the first format.
  2. 2 . The method of claim 1 , wherein accessing the first target component using the number of address bits having the second format further comprises: accessing a first address of the target component using a first set of address bits having the second format; and sequentially accessing a second address of the target component using a set of address bits having the second format by toggling an address signal associated with the first target component to indicate a flipped bit between the first and second sets of address bits.
  3. 3 . The method of claim 1 , wherein converting the format of the number of address bits at the first address encoder further comprises: converting a first portion of the number of address bits from the first format to the second format, while a second portion of the number of address bits is not converted to the second format.
  4. 4 . The method of claim 1 , further comprising: receiving a third access request with address bits having the first format to access a second target component, wherein the second target component is not compatible with access via address bits having the second format; converting, at a second address encoder, a format of the address bits of the third access request from the first format to the second format; converting, at a first address decoder, the format of the address bits of the third access request from the second format back to the first format prior to transferring the third access request to the second target component; and transferring, to the second target component, the third access request with the address bits having the first format to cause the third access request to be executed at the target component with the address bits in the first format.
  5. 5 . The method of claim 1 , wherein the first target component is further coupled to a second selection component, wherein the method further comprises: receiving, at the second selection component, a plurality of access requests that are encoded at different address encoders; and selectively transferring, at the second selection component, a number of address bits of a respective one of the plurality of access requests to the first target component.
  6. 6 . An apparatus, comprising: a first address encoder; a first selection component coupled to the first address encoder, the first selection component configured to selectively transfer a first access request or a second access request to the first address encoder in response to receipt of the first and second access requests respectively to access a target component; the first address encoder configured to convert, to encode a first number of address bits of the first access request or the second access request, the first number of address bits having a first format to a second format, wherein the second format corresponds to a reduced Hamming distance binary code format that involves a reduced number of toggles in accessing the target component than using the first format; and a second selection component configured to: receive a plurality of access requests including the first access request or the second access request with the first number of address bits having the converted format; and selectively transfer one of the plurality of access requests to the target component to access the target component via execution of the one of the plurality of access requests; and wherein the second selection component is further configured to convert, to decode a third number of address bits of a respective access request of the plurality of access requests, the third number of address bits from the second format back to the first format.
  7. 7 . The apparatus of claim 6 , wherein the first address encoder is configured to convert a first portion of the first number of address bits from the first format to the second format, while a second portion of the first number of address bits is not converted to the second format.
  8. 8 . The apparatus of claim 6 , further comprising a second address encoder configured to: receive a third access request to access the target component; convert, to encode a second number of address bits of the third access request, the second number of address bits having the first format to the second format; and transfer the third access request having the converted format to the second selection component.
  9. 9 . The apparatus of claim 6 , wherein at least two access requests of the plurality of access requests are received at the second selection component from different address encoders.
  10. 10 . The apparatus of claim 6 , wherein address bits of at least two access requests of the plurality of access requests received at the second selection component have different formats.
  11. 11 . The apparatus of claim 6 , wherein the first number of address bits comprises a plurality of sets of address bits respectively corresponding to a plurality of addresses of the target component that are to be sequentially accessed via the first number of address bits.
  12. 12 . The apparatus of claim 11 , wherein respective binary values of two sets of address bits of the first number of address bits differ in a single bit position.
  13. 13 . The apparatus of claim 6 , wherein the reduced Hamming distance binary code format is a reflected binary code (RBC) format, a Johnson ring binary code format, or a unit-distance code format, or any combination thereof.
  14. 14 . A system, comprising: a plurality of initiator components configured to issue respective access requests to access at least one of a plurality of target components; an intermediate component coupled to the plurality of initiator components and the plurality of target components, the intermediate component configured to: in response to receipt of a first access request to access the first target component from a first initiator component of the plurality of target components, wherein the first target component is compatible with access via address bits having a first format corresponding to a reduced Hamming distance binary code format: convert a first number of address bits of the first access request and having a second format to the first format; and transfer the first number of address bits having the converted format to the first target component to cause the first target component to be accessed using the first number of address bits having the converted format; and in response to receipt of a second access request to access the second target component from a second initiator component of the plurality of target components, wherein the second target component is not compatible with access via address bits having the first format; convert a second number of address bits of the second access request and having a second format to the first format; convert the second number of address bits of the second access request and having the first format to the second format prior to the second access request being received at the second target component; and transfer the second number of address bits having the converted format to the second target component to cause the second target component to be accessed using the second number of address bits having the second format.
  15. 15 . The system of claim 14 , wherein the intermediate component further comprises an address decoder directly coupled to at least one of the plurality of initiator components or the plurality of target components, the address decoder configured to convert a third number of address bits of a third access request generated at the one of the plurality of initiator components to the first format.
  16. 16 . The system of claim 14 , wherein the intermediate component is configured to: receive a third access request to access the second target component and including a number of address bits having the second format; and transfer the third access request having the second format to the second target component as is to cause the second target component to be accessed using the third access request having the second format.
  17. 17 . The system of claim 14 , wherein the intermediate component is configured to: receive a third access request to access the first target component and including a third number of address bits having the second format; and convert, at different address encoders of the intermediate component, respective formats of the first number of address bits and the third number of address bits to the first format.
  18. 18 . The system of claim 14 , wherein: the system is a System-on-Chip (SoC); and the plurality of target components comprises one or more initiator ports, loopback ports, input/output (I/O) ports of an initiator connector, or any combination thereof.
  19. 19 . A method, comprising: selectively transferring, from a first selection component and responsive to receiving a first access request and a second access request respectively to access a first target component, a number of address bits of the first access request or the second access request to a first address encoder; converting, at the first address encoder, a format of the number of address bits from a first format to a second format, wherein the second format corresponds to a reduced Hamming distance binary code format that involves a reduced number of toggles in accessing the first target component than using the first format; and accessing the first target component using the number of address bits having the second format, wherein the method further comprises: receiving a third access request with address bits having the first format to access a second target component, wherein the second target component is not compatible with access via address bits having the second format; converting, at a second address encoder, a format of the address bits of the third access request from the first format to the second format; converting, at a first address decoder, the format of the address bits of the third access request from the second format back to the first format prior to transferring the third access request to the second target component; and transferring, to the second target component, the third access request with the address bits having the first format to cause the third access request to be executed at the target component with the address bits in the first format.
  20. 20 . An apparatus, comprising: a first address encoder; a first selection component coupled to the first address encoder, the first selection component configured to selectively transfer a first access request or a second access request to the first address encoder in response to receipt of the first and second access requests respectively to access a target component; the first address encoder configured to convert, to encode a first number of address bits of the first access request or the second access request, convert a first portion of the first number of address bits from the first format to the second format, while a second portion of the first number of address bits is not converted to the second format, wherein the second format corresponds to a reduced Hamming distance binary code format that involves a reduced number of toggles in accessing the target component than using the first format; and a second selection component configured to: receive a plurality of access requests including the first access request or the second access request with the first number of address bits having the converted format; and selectively transfer one of the plurality of access requests to the target component to access the target component via execution of the one of the plurality of access requests.

Description

PRIORITY INFORMATION This application claims the benefits of U.S. Provisional Application No. 63/588,524, filed on Oct. 6, 2023, the contents of which are incorporated herein by reference. TECHNICAL FIELD Embodiments of the disclosure relate generally to reduced power addressing. BACKGROUND Various types of electronic devices such as digital logic circuits and memory systems may store and process data. A digital logic circuit is an electronic circuit that processes digital signals or binary information, which can take on two possible values (usually represented as 0 and 1). The digital logic circuit can use logic gates to manipulate and transform the digital signals or binary information. Digital logic circuits can be used in a wide range of electronic devices including, for example, computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logical operations on digital inputs to generate digital outputs, and, in some instances, can be combined to form more complex circuits to perform more complex operations. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates an example portion of a computing system configured to perform reduced power addressing in accordance with some embodiments of the present disclosure. FIG. 2 illustrates an example portion of a computing system configured to perform reduced power addressing in accordance with various embodiments of the present disclosure. FIG. 3 illustrates another example portion of a computing system configured to perform reduced power addressing in accordance with various embodiments of the present disclosure. FIG. 4 is a flow diagram corresponding to a method for performing reduced power addressing in accordance with various embodiments of the present disclosure. DETAILED DESCRIPTION Aspects of the present disclosure are directed to reduced power addressing within electronic systems. Various components within an electronic system, such as a System-on-Chip (SoC), can be accessed via respective address buses. Such components can include memory devices (e.g., arrays), interface connectors having ports, buses etc. that have addresses that can be accessed via access requests originated from different entities (e.g., host processors). In some examples, these addresses having successive addresses (e.g., consecutive physical addresses) can be or need to be sequentially accessed as opposed to those addresses that are not necessarily sequentially accessed despite having successive addresses. The latter access scheme is known as “random access”, in which addresses can be independently accessed without the need to traverse through all the addresses sequentially from one end to the other end (e.g., from the beginning to the end or vice versa). In A sequential access scheme, an address signal can be toggled to switch from one set of address bits (to access one portion of the memory) to the other set of address bits (to access a subsequent portion of the memory). In this approach, a quantity of toggles occurred in accessing the memory can often be based on a number of particular data values to be switched (e.g., “0” to “1” or “1” to “0”) between two sets of address bits, and each toggle can incur a power consumption. Therefore, the increased quantity of toggles can undesirably increase the power consumed in accessing the memory cells and it is desired to reduce the power consumption associated with sequentially accessing any addresses within the computing system. As described in more detail herein, aspects of the present disclosure provide an intermediate component coupled between initiator components (that generate and issue access requests and simply referred to as “initiators”) and target components (that are to be accessed via the access requests and simply referred to as “targets”) with capability of encoding address bits to have a reduced Hamming distance code format. The intermediate component can be “interconnects” (e.g., Network-on-Chip (NOC), fabric interconnect, ring interconnect, bus interconnect, etc.), one or more buses, or transmission lines, or any combination thereof, that connects multiple/different entities (such as parts/components/modules, etc.) and serves as data paths between the entities. As used herein, the term “reduced Hamming distance binary code” refers to binary code having a reduced Hamming distance between two consecutive values. Although embodiments are not so limited, the reduced Hamming distance binary code can be reflected binary code (RBC) code (alternative referred to as “Gray code”), Johnson ring (cyclic) code, etc., as compared to a binary code that is not tailored to reduce a Hamming distance (alternatively referred to as “non-reduced Hamming distance binary code”