US-12625628-B2 - Controller and storage device

US12625628B2US 12625628 B2US12625628 B2US 12625628B2US-12625628-B2

Abstract

Data storage devices and controllers are disclosed. In an embodiment of the disclosed technology, an occupied logical memory address for loading an overlay code stored in a memory into a buffer memory is allocated and set in advance, and the loading of the overlay code is performed using the occupied logical memory address. Therefore, the overlay code can be loaded without allocating in advance a buffer area of the buffer memory, and thus the buffer memory may be efficiently used and the loading of the overlay code may be effectively performed.

Inventors

Baek Gyun CHOI

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260512
Application Date: 20240430
Priority Date: 20231212

Claims (20)

1 . A storage device comprising: a first memory configured to store a plurality of codes including a plurality of overlay codes and a plurality of non-overlay codes, wherein the plurality of non-overlay codes is used more frequently than the plurality of overlay codes; a second memory including a plurality of buffer areas configured to be loaded with the plurality of codes; and a controller configured to: allocate, in advance, at least one occupied logical memory address for loading the plurality of codes, wherein, upon allocation, the at least one occupied logical memory address is not connected to the plurality of buffer areas; connect a first occupied logical memory address of the at least one occupied logical memory address to at least one of the plurality of buffer areas upon loading a first overlay code of the plurality of overlay codes; and load the first overlay code into the at least one buffer area connected to the first occupied logical memory address.
2 . The storage device according to claim 1 , wherein upon completion of use of the first overlay code, the controller releases a connection between the first occupied logical memory address and the at least one buffer area.
3 . The storage device according to claim 2 , wherein upon loading of a second overlay code after the completion of use of the first overlay code, the controller connects the first occupied logical memory address to at least one of the plurality of buffer areas, and loads the second overlay code into the at least one buffer area connected to the first occupied logical memory address.
4 . The storage device according to claim 3 , wherein the at least one buffer area loaded with the first overlay code is different from the at least one buffer area loaded with the second overlay code.
5 . The storage device according to claim 2 , wherein, after releasing the connection between the first occupied logical memory address and the at least one buffer area, the controller maintains a setting of the first occupied logical memory address.
6 . The storage device according to claim 1 , wherein, after completion of use of the first overlay code, the controller maintains a connection between the first occupied logical memory address and the at least one buffer area.
7 . The storage device according to claim 6 , wherein, upon loading a second overlay code, the controller loads the second overlay code into the at least one buffer area connected to the first occupied logical memory address.
8 . The storage device according to claim 6 , wherein, in a case that a remaining capacity of the plurality of buffer areas in the second memory is smaller than a preset value, the controller releases a connection between the first occupied logical memory address and the at least one buffer area.
9 . The storage device according to claim 1 , wherein, upon loading a second overlay code during a use of the first overlay code, the controller connects a second occupied logical memory address to at least one of the plurality of buffer areas, and loads the second overlay code into the at least one buffer area connected to the second occupied logical memory address.
10 . The storage device according to claim 9 , wherein, in a case that a remaining capacity of the plurality of buffer areas is equal to or larger than a preset value in a state in which a use of the first overlay code is completed and the second overlay code is being used, the controller maintains connection between the first occupied logical memory address and the at least one buffer area.
11 . The storage device according to claim 1 , wherein, upon loading at least one of the plurality of non-overlay codes, the controller allocates an unoccupied logical memory address other than the at least one occupied logical memory address, connects the unoccupied logical memory address to at least one of the plurality of buffer areas, and loads the at least one non-overlay code into the at least one buffer area connected to the unoccupied logical memory address.
12 . The storage device according to claim 11 , wherein the occupied logical memory address is fixed, and the unoccupied logical memory address is variable.
13 . The storage device according to claim 1 , wherein the at least one buffer area into which the first overlay code is loaded at a first time point is different from the at least one buffer area into which the first overlay code is loaded at a second time point.
14 . A controller comprising: a buffer memory including a plurality of buffer areas configured to be loaded with a plurality of codes; and a processor configured to: allocate, in advance, at least one occupied logical memory address in the buffer memory for loading the plurality of codes, wherein, upon allocation, the at least one occupied logical memory address is not connected to the plurality of buffer areas; connect a first occupied logical memory address to at least one of the plurality of buffer areas upon loading a first code; and load the first code into the at least one buffer area connected to the first occupied logical memory address.
15 . The controller according to claim 14 , wherein, upon loading a second code after completion of a use of the first code, the processor loads the second code into the at least one buffer area connected to the first occupied logical memory address.
16 . The controller according to claim 14 , wherein, upon loading a second code during a use of the first code, the processor connects a second occupied logical memory address to at least one of the plurality of buffer areas, and loads the second code into the at least one buffer area connected to the second occupied logical memory address.
17 . The controller according to claim 14 , wherein, upon loading a third code, the processor connects an unoccupied logical memory address other than the at least one occupied logical memory address to at least one of the plurality of buffer areas, and loads the third code into the at least one buffer area connected to the at least one unoccupied logical memory address.
18 . The controller according to claim 14 , wherein the first occupied logical memory address used for loading the first code is fixed, and the at least one buffer area into which the first code is loaded is variable.
19 . A controller configured to: allocate in advance at least one occupied logical memory address used for loading a plurality of overlay codes, wherein, upon allocation, the at least one occupied logical memory address is not connected to a plurality of buffer areas; and upon loading at least one of the plurality of overlay codes, load the at least one overlay code into at least one first buffer area of the plurality of buffer areas connected to the at least one occupied logical memory address, wherein a plurality of non-overlay codes is used by the controller more frequently than the plurality of overlay codes.
20 . The controller according to claim 19 , wherein, upon loading a non-overlay code, the controller uses an unoccupied logical memory address other than the at least one occupied logical memory address, and loads the non-overlay code into at least one second buffer area connected to the unoccupied logical memory address.

Description

CROSS-REFERENCE TO RELATED APPLICATION This patent document claims the priority and benefits of Korean Patent Application No. 10-2023-0179399 filed in on Dec. 12, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD Various embodiments of the disclosed technology generally relate to a controller and a storage device. BACKGROUND A storage device may include a memory device each of which includes a plurality of memory cells configured to store data. The storage device may include a controller that controls operations of the memory, such as writing or reading data to or from the memory device or erasing data stored in the memory. For example, the controller may control the memory by executing firmware. In some cases, the firmware may be stored in the one or more memory device included in the storage device. SUMMARY Various embodiments of the disclosed technology are directed to providing measures capable of efficiently using a buffer area available to be used by a controller included in a storage device and improving the operation efficiency of firmware loaded into the buffer area. In an embodiment, a storage device may include: a first memory configured to store a plurality of codes including a plurality of overlay codes and a plurality of non-overlay codes, wherein the plurality of non-overlay codes is used more frequently than the plurality of overlay codes; a second memory including a plurality of buffer areas configured to be loaded with the plurality of codes; and a controller configured to: allocate, in advance, at least one occupied logical memory address for loading the plurality of codes; connect a first occupied logical memory address of the at least one occupied logical memory address to at least one of the plurality of buffer areas upon loading a first overlay code of the plurality of overlay codes; and load the first overlay code into the at least one buffer area connected to the first occupied logical memory address. In an embodiment, a controller may include: a buffer memory including a plurality of buffer areas configured to be loaded with a plurality of codes; and a processor configured to: allocate, in advance, at least one occupied logical memory address in the buffer memory for loading the plurality of codes; connect a first occupied logical memory address to at least one of the plurality of buffer areas upon loading a first code; and load the first code into the at least one buffer area connected to the first occupied logical memory address. In an embodiment, a controller may be configured to: allocate in advance at least one occupied logical memory address used for loading a plurality of overlay codes; and upon loading at least one of the plurality of overlay codes, load the at least one overlay code into at least one first buffer area connected to the at least one occupied logical memory address, wherein the plurality of non-overlay codes is used by the controller more frequently than the plurality of overlay codes. In an embodiment, a storage device may include: a first memory configured to store a plurality of codes which include a plurality of overlay codes and a plurality of non-overlay codes; a second memory including a plurality of buffer areas into which the plurality of codes are loaded; and a controller configured to set at least one occupied logical memory address which is allocated in advance for loading the plurality of codes, connect a first occupied logical memory address to at least one of the plurality of buffer areas when loading a first overlay code, and load the first overlay code into the at least one buffer area which is connected to the first occupied logical memory address. In an embodiment, a controller may include: a buffer memory including a plurality of buffer areas into which a plurality of codes are loaded; and a processor configured to set at least one occupied logical memory address which is allocated in advance for loading the plurality of codes, connect a first occupied logical memory address to at least one of the plurality of buffer areas when loading a first code, and load the first code into the at least one buffer area which is connected to the first occupied logical memory address. In an embodiment, a controller may be configured to allocate and set in advance at least one occupied logical memory address used for loading a plurality of overlay codes, and when loading at least one of the plurality of overlay codes, load the at least one overlay code into at least one first buffer area which is connected to the at least one occupied logical memory address. According to an embodiments of the disclosed technology, it is possible to efficiently use a buffer area used by a controller and improve the operation efficiency of firmware executed by being loaded into the buffer area. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an example configuration of a storage device based on an embodiment of the disclosed