US-12625629-B2 - Host interface for memory interconnect DRAM + NAND system solution

Abstract

Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.

Inventors

• Rohit Sehgal
• Vishal TANNA
• Krishna SIDDHAREDDY
• Eishan MIRAKHUR

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240307

Claims (19)

1. 1 . A system comprising: non-volatile memory; dynamic random-access memory (DRAM); a host interface configured to communicate with a host computing device; a memory controller operatively coupled to the host interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the host interface; and a task processor operatively coupled to the non-volatile memory and the DRAM; and an ethernet adapter being configured to receive data as NVME data packets; wherein the non-volatile memory, the DRAM the memory controller, the task processor and the ethernet adapter are mounted on a printed circuit board; wherein the task processor is configured to store the received data in the non-volatile memory and then transfer the received data to the DRAM; and wherein the memory controller is configured to switch between modes of operation including a first mode of operation in which the task processor has access to the data stored in the DRAM and a second mode of operation in which the host computing device has access to the data stored in the DRAM through the host interface.
2. 2 . The system of claim 1 , wherein, in the first mode of operation, the task processor is configured to obtain data from the non-volatile memory, process the data obtained from the non-volatile memory, and then store the data obtained from the non-volatile memory in the DRAM.
3. 3 . The system of claim 1 , wherein the processing of the data by the task processor includes sorting or indexing the data or performing another user defined task so that the data is stored in the DRAM in a form that is accessible from the DRAM by the host computing device.
4. 4 . The system of claim 1 , wherein, in the first mode of operation, the task processor is configured to transfer the data stored in the DRAM to the non-volatile memory.
5. 5 . The system of claim 1 , wherein, in the second mode of operation, the memory controller is configured to obtain the data stored in the DRAM and provide the data to the host computing device through the host interface.
6. 6 . The system of claim 1 , wherein, in the second mode of operation, the memory controller is configured to obtain the data stored in the DRAM and provide the data to the host computing device through the host interface while other data is being stored in the non-volatile memory through operation performed by the task processor.
7. 7 . The system of claim 1 , wherein: in the second mode of operation, the memory controller is configured to write updated data into the DRAM, the updated data resulting from processing of the data by the host computing device, and the updated data written into the DRAM being accessible by the task processor when the memory controller switches from the second mode of operation to the first mode of operation.
8. 8 . The system of claim 1 , further comprising a printed circuit board, wherein each of the non-volatile memory, the DRAM, the memory controller and the task processor is formed by at least one integrated circuit (IC) chip; and wherein each of the IC chips respectively forming the non-volatile memory, the DRAM, the memory controller and the task processor is mounted on the printed circuit board.
9. 9 . A method of operating a system comprising non-volatile memory, dynamic random-access memory (DRAM), a host interface configured to communicate with a host computing device, a memory controller operatively coupled to the host interface and the DRAM, a task processor (i) operatively coupled to the non-volatile memory and the DRAM and (ii) configured to store the received data in the non-volatile memory and then transfer the received data to the DRAM, and an ethernet adapter being configured to receive data as NVME packets, the method comprising: controlling a transfer of information between the DRAM and the host computing device through the host interface by operation of the memory controller; controlling a transfer of information between the DRAM and the task processor; and switching between two modes of operation including a first mode of operation in which the task processor has access to data stored in the DRAM and a second mode of operation in which the host computing device has access to the data stored in the DRAM through the host interface; wherein the non-volatile memory, the DRAM the memory controller, the task processor and the ethernet adapter are mounted on a printed circuit board.
10. 10 . The method of claim 9 , wherein, in the first mode of operation, the task processor performs obtaining data from the non-volatile memory, processing the data obtained from the non-volatile memory, and then storing the data obtained from the non-volatile memory in the DRAM.
11. 11 . The method of claim 10 , wherein the processing of the data by the task processor includes sorting or indexing the data or performing another user defined task so that the data is stored in the DRAM in a form that is accessible from the DRAM by the host computing device.
12. 12 . The method of claim 9 , wherein the method further comprises, in the first mode of operation, transferring the data stored in the DRAM to the non-volatile memory.
13. 13 . The method of claim 9 , wherein, in the second mode of operation, the memory controller performs obtaining the data stored in the DRAM and providing the data to the host computing device through the host interface.
14. 14 . The method of claim 9 , wherein, in the second mode of operation, the memory controller performs obtaining the data stored in the DRAM and providing the data to the host computing device through the host interface while other data is being stored in the non-volatile memory through operation performed by the task processor.
15. 15 . The method of claim 9 , wherein: in the second mode of operation, updated data is written into the DRAM, the updated data resulting from processing of the data by the host computing device, and the updated data written into the DRAM being accessible by the task processor when the memory controller switches from the second mode of operation to the first mode of operation.
16. 16 . The method of claim 9 , further comprising providing a printed circuit board; wherein each of the non-volatile memory, the DRAM, the memory controller and the task processor is formed by at least one IC chip; and wherein each of the integrated circuit (IC) chips respectively forming the non-volatile memory, the DRAM, the memory controller and the task processor is mounted on the printed circuit board.
17. 17 . A device comprising: a Peripheral Component Interconnect Express (PCIe) interface configured to communicate with a host computing device; a printed circuit board; a first integrated circuit (IC) chip forming non-volatile memory; a second IC chip forming dynamic random-access memory (DRAM); a third IC chip forming a compute express link (CXL) memory controller operatively coupled to the PCIe interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the PCIe interface; a fourth IC chip forming a task processor operatively coupled to the non-volatile memory and the DRAM; and an ethernet adapter being configured to receive data as NVME data packets; wherein the first IC chip, the second IC chip, the third IC chip, the fourth IC chip and the ethernet adapter are mounted on the printed circuit board; and wherein the task processor is configured to store the received data in the non-volatile memory and then transfer the received data to the DRAM.
18. 18 . The device of claim 17 , further comprising an ethernet adapter, the ethernet adapter being mounted on the printed circuit board and being configured to receive data as non-volatile memory express (NVME) data packets; wherein the task processor is configured to buffer the received data in the DRAM and then transfer the buffered data from the DRAM to the non-volatile memory.
19. 19 . The device of claim 17 , wherein the PCIe interface is configured to receive data from the host computing device; wherein the DRAM is configured to store the data received by the PCIe interface; and wherein the task processor is configured to transfer the data stored in the DRAM to the non-volatile memory.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit to U.S. Provisional Patent Application No. 63/491,484, filed Mar. 21, 2023, the disclosure is incorporated herein by reference in its entirety. FIELD OF TECHNOLOGY The present disclosure relates generally to semiconductor memory devices and methods, and systems. BACKGROUND Memory devices (also referred to as memory media devices) are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read, or sense, the state of one or more memory cells within the memory device. To store information, a component may write, or program, one or more memory cells within the memory device to corresponding states. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), DRAM, synchronous dynamic RAM (SDRAM), static RAM (SRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed states over time unless they are periodically refreshed by an external power source. SRAM memory may maintain their programmed states for the duration of the system being powered on. Non-volatile memory cells, for example, a solid-state drive (SSD) comprised of Not-And (NAND) memory cells may maintain their programmed states for extended periods of time even in the absence of an external power source. Memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and/or instructions for use by the host while the computer or other electronic system is operating. For example, data, commands, control signals and/or instructions can be transferred between the host and the memory device(s) during operation of a computing or other electronic system. A controller, referred to as a memory controller”, may be used to manage the transfer of data, commands, and/or instructions between the host and the memory devices. The commands received by the memory controller from the host may include read commands and write commands. When the host sends a write command to the memory controller, the host system can still run independently. However, when the host sends a read command to the memory controller, an application run on a central processing unit (CPU) connected to the host may become disadvantageously locked up or delayed while waiting for data to be acquired in response to the sent read command. BRIEF DESCRIPTION OF THE DRAWINGS Illustrative embodiments may take form in various components and arrangements of components. Illustrative embodiments are shown in the accompanying drawings, throughout which like reference numerals may indicate corresponding or similar parts in the various drawings. The drawings are only for purposes of illustrating the embodiments and are not to be construed as limiting the disclosure. Given the following enabling description of the drawings, the novel aspects of the present disclosure should become evident to a person of ordinary skill in the relevant art(s). FIG. 1 illustrates an example computing system having a printed circuit board including mounted integrated circuit (IC) chips respectively implementing at least a DRAM, a non-volatile memory, a memory controller, and a task processor according to some example embodiments of the present disclosure. FIG. 2 illustrates a flowchart depicting a process performed by the computing system according to some example embodiments of the present disclosure. FIG. 3 illustrates example blocks of the process performed by the computing system the computing system having the printed circuit board including mounted IC chips respectively implementing at least the DRAM, the non-volatile memory, the memory controller, and the task processor according to some example embodiments of the present disclosure. FIG. 4 illustrates functional block diagram showing a computing system according to a conventional implementation. DETAILED DESCRIPTION The present disclosure describes systems, apparatuses, and methods related to a task processor processing data received through an ethernet or Wi-Fi port and storing the received data directly in non-volatile memory such that the host computing device does not have to perform the tasks associated with receiving and storing the data in the non-volatile memory to thereby free up the host computing device to execute other instructions to perform other tasks. The task processor obtains the data fro