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US-12625630-B2 - Memory storage with selected performance mode

US12625630B2US 12625630 B2US12625630 B2US 12625630B2US-12625630-B2

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Inventors

  • Shunichi IGAHARA
  • Toshikatsu Hida
  • Riki SUZUKI
  • Takehiko Amaki
  • Suguru NISHIKAWA
  • Yoshihisa Kojima

Assignees

  • KIOXIA CORPORATION

Dates

Publication Date
20260512
Application Date
20240730
Priority Date
20170922

Claims (20)

  1. 1 . A memory system connectable to a host, the memory system comprising: a nonvolatile memory including a plurality of memory cells; and a controller configured to write data to the nonvolatile memory in either a first mode or a second mode, a number of bits of data written in a memory cell in the second mode being larger than a number of bits of data written in a memory cell in the first mode, wherein the controller is further configured to: determine a size of a first region of the nonvolatile memory for writing data in the first mode, based on an amount of used storage with respect to a full storage capacity of the memory system; write first data, which is received from the host, into the first region in the first mode; upon a size of an available area in the first region being smaller than a first threshold, determine to write at least part of the first data stored in the first region into a second region of the nonvolatile memory in the second mode; and write the at least part of the first data stored in the first region into the second region in the second mode.
  2. 2 . The memory system according to claim 1 , wherein the first data include a plurality of pieces of data, and the controller is further configured to prioritize keeping a first piece of the plurality of pieces of data having a first access frequency in the first region over a second piece of the plurality of pieces of data having a second access frequency lower than the first access frequency.
  3. 3 . The memory system according to claim 2 , wherein the prioritization is based on information received from the host.
  4. 4 . The memory system according to claim 1 , wherein the first data include a plurality of pieces of data, and the controller is further configured to: in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the first region and the second region, a write destination region for each of the plurality of pieces of data based on an access frequency of the each of the plurality of pieces of data.
  5. 5 . The memory system according to claim 4 , wherein information about the access frequency is received from the host.
  6. 6 . The memory system according to claim 4 , wherein the controller is further configured to calculate the access frequency.
  7. 7 . The memory system according to claim 4 , wherein the controller is configured to: select the first region as the write destination region for a piece with a first access frequency among the plurality of pieces of data; and select the second region as the write destination region for a piece with a second access frequency among the plurality of pieces of data, the second access frequency being lower than the first access frequency.
  8. 8 . The memory system according to claim 1 , wherein the first data include a plurality of pieces of data, and the controller is further configured to: in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the first region and the second region, a write destination region for a first piece of the plurality of pieces of data based on an access frequency of the first piece of data.
  9. 9 . The memory system according to claim 8 , wherein the controller is further configured to: in a case where the access frequency of the first piece of data is higher than or equal to a second threshold, select the first region as the write destination region for the first piece of the plurality of pieces of data; and in a case where the access frequency of the first piece of data is lower than the second threshold, select the second region as the write destination region for the first piece of the plurality of pieces of data.
  10. 10 . The memory system according to claim 1 , wherein the first data include a plurality of pieces of data, and the controller is further configured to: in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the plurality of pieces of data, a first piece of data to write into the first region based on an access frequency of at least one of the plurality of pieces of data.
  11. 11 . The memory system according to claim 10 , wherein the controller is configured to: select a piece of data with high access frequency as the first piece of data.
  12. 12 . The memory system according to claim 10 , wherein the controller is configured to: select a piece of data with the access frequency higher than a second threshold as the first piece of data.
  13. 13 . The memory system according to claim 1 , wherein the first data include a plurality of pieces of data, and the controller is further configured to: in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the plurality of pieces of data, a first piece of data to write into the second region based on an access frequency of at least one of the plurality of pieces of data.
  14. 14 . The memory system according to claim 13 , wherein the controller is configured to: select a piece of data with low access frequency as the first piece of data.
  15. 15 . The memory system according to claim 13 , wherein the controller is configured to: select a piece of data with the access frequency lower than a second threshold as the first piece of data.
  16. 16 . The memory system according to claim 1 , wherein the second region is for writing data in the second mode.
  17. 17 . The memory system according to claim 1 , wherein the amount of used storage with respect to the full storage capacity of the memory system is a total number of logical addresses mapped to physical addresses of the nonvolatile memory.
  18. 18 . The memory system according to claim 1 , wherein the used storage of the memory system is a ratio of (A) a total number of logical addresses mapped to physical addresses of the nonvolatile memory to (B) an entire logical address space of the memory system, and the controller is further configured to manage the ratio.
  19. 19 . The memory system according to claim 1 , wherein the controller is configured to write the at least part of the first data stored in the first region into the second region in response to the first region reaching its full capacity.
  20. 20 . The memory system according to claim 1 , wherein the first mode is a single-level-cell (SLC) mode and the second mode is a quad-level-cell (QLC) mode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 18/343,835, filed Jun. 29, 2023 (now U.S. Pat. No. 12,086,439), which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 17/028,087 filed Sep. 22, 2020 (now U.S. Pat. No. 11,733,888), which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 16/117,262 (now U.S. Pat. No. 10,824,353), filed Aug. 30, 2018, which is based upon and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2017-182025, filed Sep. 22, 2017, the entire contents of each of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a memory system including a nonvolatile memory. BACKGROUND In recent years, memory systems including a nonvolatile memory are widely used. As a type of the memory systems, a solid state drive (SSD) including a NAND flash memory is known. SSDs are used as a main storage of various computing devices. Since the tolerable maximum number of program/erase (P/E) cycles for a nonvolatile memory such as a NAND flash memory is limited, the nonvolatile memory may fail when the P/E cycles exceeding the limited number are executed. Furthermore, in a nonvolatile memory, when the number of bits stored in each memory cell increases, a storage capacity (specifically, memory density) increases, and a time required to write data in the nonvolatile memory and a time required to read data from the nonvolatile memory both become longer. Recently, memory systems configured to write data in a nonvolatile memory by selectively using a single level cell (SLC) mode to store one bit data in one memory cell and a multi level cell (MLC) mode to store two or more bit data in one memory cell have been developed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of the structure of a memory system according to a first embodiment. FIG. 2 is a block diagram showing an example of the structure of management data stored in DRAM provided with the memory system of the first embodiment. FIG. 3 shows an example of the structure of a lookup table (LUT) used in the memory system of the first embodiment. FIG. 4 shows an example of the structure of a block—number of P/E cycles table used in the memory system of the first embodiment. FIG. 5 shows an example of the structure of an LBA range—access frequency table used in the memory system of the first embodiment. FIG. 6 shows an example of the structure of a block—valid data amount table used in the memory system of the first embodiment. FIG. 7 shows an example of the structure of a block—cold data ratio table used in the memory system of the first embodiment. FIG. 8 shows an example of the structure of an LBA range—write mode table used in the memory system of the first embodiment. FIG. 9 shows an example of the structure of a name space ID—write mode table used in the memory system of the first embodiment. FIG. 10 shows an example of the structure of a stream ID—write mode table used in the memory system of the first embodiment. FIG. 11 shows characteristics of write modes used in the memory system of the first embodiment. FIG. 12 shows an example of storage capacities of a NAND flash memory corresponding to write modes of FIG. 11. FIG. 13 shows switching a write mode to another write mode with larger number of bits per cell in the memory system of the first embodiment. FIG. 14 shows switching a write mode to another write mode with smaller number of bits per cell in the memory system of the first embodiment. FIG. 15 shows an example of the NAND flash memory of the memory system of the first embodiment including an SLC mode only block group and a TLC/QLC shared block group. FIG. 16 shows an example in which SLC mode is selected when user data is written in the memory system of the first embodiment. FIG. 17 shows an example in which TLC mode is selected when user data is written in the memory system of the first embodiment. FIG. 18 shows an example in which QLC mode is selected where user data is written in the memory system of the first embodiment. FIG. 19 shows physical addresses mapped in a logical address space in the memory system of the first embodiment. FIG. 20 shows logical addresses mapped in a physical address space in the memory system of the first embodiment. FIG. 21 shows an example of transition of write performance corresponding to switching of write modes of user data by the memory system of the first embodiment. FIG. 22 shows an example in which LUT (address conversion data) is written in the NAND flash memory by the memory system of the first embodiment. FIG. 23 shows transition of write performance corresponding to switching of write modes of user data and switching of write modes of LUT by the memory system of the first embodiment. FIG. 24 shows an example of