US-12625631-B2 - Parameter value optimization in a memory sub-system

Abstract

A processing device, operatively coupled with a memory device, determines a current workload characteristic of the memory device. The processing device further determines, by a trainable classifier processing the current workload characteristic, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device. The processing device further configures the firmware component of the memory device with the first set of one or more parameter values.

Inventors

• Aswin Thiruvengadam
• Sundararajan Sankaranarayanan
• Ahmet Kaya
• Josh Hieb
• Jay Sarkar

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240716

Claims (20)

1. 1 . A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: determining a current number of memory access operations performed on the memory device; determining, by a trainable classifier, based on the current number of memory access operations, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device; and configuring a firmware component of the memory device with the first set of one or more parameter values.
2. 2 . The system of claim 1 , wherein the operations further comprise: identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current number of memory access operations performed on the memory device; and identifying a second set of one or more parameter values associated with the identified record, wherein the second set of one or more parameter values satisfies the threshold workload criterion.
3. 3 . The system of claim 1 , wherein the threshold workload criterion comprises at least one of: a target read operation latency, a target write operation latency, a target read operation bandwidth, or a target write operation bandwidth.
4. 4 . The system of claim 1 , wherein the operations further comprise: inputting the current number of memory access operations into the trainable classifier.
5. 5 . The system of claim 1 , wherein the trainable classifier comprises at least one of: a decision tree, a machine learning model, or a regression machine learning model.
6. 6 . The system of claim 1 , wherein the one or more parameter values comprise a number of read operations allowed during a program suspend operation.
7. 7 . The system of claim 1 , wherein the one or more parameter values comprise a number of suspend operations allowed during a program operation.
8. 8 . The system of claim 1 , wherein the threshold workload criterion comprises a target performance characteristic represented by a desired memory access operation latency.
9. 9 . The system of claim 1 , wherein the threshold workload criterion comprises a target performance characteristic represented by a desired memory access operation bandwidth.
10. 10 . The system of claim 1 , wherein the threshold workload criterion comprises a target performance characteristic represented by a threshold time period for completing a program operation.
11. 11 . The system of claim 1 , wherein the threshold workload criterion comprises a target performance characteristic represented by a threshold time period for restricting a program operation.
12. 12 . A method comprising: determining a current number of memory access operations performed on a memory device; determining, by a trainable classifier, based on the current number of memory access operations, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device; and configuring a firmware component of the memory device with the first set of one or more parameter values.
13. 13 . The method of claim 12 , further comprising: identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current number of memory access operations performed on the memory device; and identifying a second set of one or more parameter values associated with the identified record, wherein the second set of one or more parameter values satisfies the threshold workload criterion.
14. 14 . The method of claim 12 , further comprising: inputting the current number of memory access operations into the trainable classifier.
15. 15 . The method of claim 12 , wherein the trainable classifier comprises at least one of: a decision tree, a machine learning model, or a regression machine learning model.
16. 16 . The method of claim 12 , wherein the one or more parameter values comprise one of: a number of read operations allowed during a program suspend operation or a number of suspend operations allowed during a program operation.
17. 17 . The method of claim 12 , wherein the threshold workload criterion comprises a target performance characteristic represented by one of: a desired memory access operation latency, a desired memory access operation bandwidth, a threshold time period for completing a program operation, or a threshold time period for restricting a program operation.
18. 18 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a current number of memory access operations performed on a memory device determining, by a trainable classifier, based on the current number of memory access operations, a first set of one or more parameter values that satisfies a threshold workload criterion; and configuring a firmware component of the memory device with the first set of one or more parameter values.
19. 19 . The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise: inputting the current number of memory access operations into the trainable classifier.
20. 20 . The non-transitory computer-readable storage medium of claim 18 , wherein the trainable classifier comprises at least one of: a decision tree, a machine learning model, or a regression machine learning model.

Description

REFERENCE TO RELATED APPLICATIONS This application claims the priority benefit of U.S. Provisional Application No. 63/527,643, filed Jul. 19, 2023, which is incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to parameter value optimization in a memory sub-system. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates an example computing system that includes a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 2 is a block diagram illustrating an example data structure described with reference to FIGS. 3-4, in accordance with some embodiments of the present disclosure. FIG. 3 is a flow diagram of an example method of performing parameter value optimization in a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 4 is a flow diagram of an example method of performing parameter value optimization in a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 5 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to parameter value optimization in a memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a not-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. A non-volatile memory device is a package of one or more dies. Each die includes one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the memory cell type, a memory cell can store one or more bits of binary information and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. Certain memory devices have memory device specifications set by industry standards, customer standards, device performance requirements, etc. For example, certain memory devices are to achieve certain performance metrics, such as a target read operation latency, a target write operation latency, a target read operation bandwidth, a target write operation bandwidth, etc. In order to achieve those performance metrics/device specifications, a firmware component of a memory device often uses a preconfigured set of parameter values that can impact the performance of the memory device. These parameter values can include, for example, the number of read operations performed during a program suspend and/or erase suspend operation; a number of suspend operations performed during a program and/or erase operation, etc. However, the set of parameter values can be determined during the design phase of the memory device (pre-manufacturing), where offline testing is performed (e.g., directly on the memory device or in a simulation environment) using various workload characteristics (e.g., various conditions under which a memory device operates, such as a particular number of memory access operations performed on the memory device, etc.). The set of parameter values can thus be identified for achieving the performance metrics/device specifications for the memory device operating at any of the various workload characteristics used during the design phase. However, when the memory device is running post-manufacturing, the memory device can experience workload characteristics that are different from the various workload characteristics used during the design phase. For example, the temperature of the memory device can affect workload characte