US-12625634-B2 - Adaptive memory partition closure time

US12625634B2US 12625634 B2US12625634 B2US 12625634B2US-12625634-B2

Abstract

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.

Inventors

Zhongguang Xu

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20241031

Claims (20)

1 . A system comprising: a memory sub-system comprising a set of memory components; and a processing device, operatively coupled to the set of memory components to perform operations comprising: storing data that associates different ranges of memory reliability values with different partition closing times; selecting, based on the data, a partition closing time for an individual portion of the set of memory components; and defining a partition of the individual portion of the set of memory components based on the partition closing time.
2 . The system of claim 1 , wherein the operations comprise: associating the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.
3 . The system of claim 2 , wherein the bin is a first bin representing a first read level threshold voltage against which the charge distribution is compared to determine the one or more logical values, and wherein the operations comprise: determining that a time interval elapsed since a collection of data was initially programmed in the partition corresponds to the partition closing time; and in response to determining that the time interval has elapsed, associating the partition with a second bin of the plurality of bins, the second bin representing a second read level threshold voltage against which the charge distribution is compared to determine the one or more logical values.
4 . The system of claim 1 , wherein the operations comprise: preventing additional data from being stored in the partition of the individual portion of the set of memory components in response to determining that a time interval has elapsed.
5 . The system of claim 1 , wherein the operations comprise: selecting a set of bin scan frequencies from a plurality of sets of bin scan frequencies based on a memory reliability value associated with the individual portion of the set of memory components.
6 . The system of claim 5 , wherein the operations comprise: selecting an individual bin scan frequency from the set of bin scan frequencies corresponding to a second bin; and determining whether to associate the partition with a third bin instead of the second bin periodically based on the individual bin scan frequency.
7 . The system of claim 1 , wherein the operations comprise: determining that a time interval elapsed since a collection of data was initially programmed in the partition corresponds to the partition closing time; and closing the partition in response to determining that the time interval elapsed to define the partition.
8 . The system of claim 7 , wherein the partition is a first partition, and wherein the operations comprise: receiving a request to write data to the individual portion of the set of memory components after the first partition has been closed; and in response to receiving the request, writing the data to a second partition of the individual portion of the set of memory components.
9 . The system of claim 8 , wherein the operations comprise: initiating a timer for the second partition in response to receiving the request; and closing the second partition in response to determining that the timer has reached the partition closing time corresponding to the individual portion of the set of memory components.
10 . The system of claim 9 , wherein a first bin of a plurality of bins represents a first read level threshold voltage against which a charge distribution is compared to determine one or more logical values, and wherein the operations comprise: associating the first partition with a second bin of the plurality of bins, the second bin representing a second read level threshold voltage against which the charge distribution is compared to determine the one or more logical values; and associating the second partition with the first bin of the plurality of bins.
11 . The system of claim 1 , wherein the individual portion is a first portion, wherein a memory reliability value is a first memory reliability value of the individual portion, wherein the partition closing time is a first partition closing time, and wherein the operations comprise: receiving a request to write data to a second portion of the set of memory components; determining a second memory reliability value associated with the second portion of the set of memory components; and selecting a second partition closing time for the second portion of the set of memory components based on the second memory reliability value.
12 . The system of claim 11 , wherein the second partition closing time is shorter than the first partition closing time.
13 . The system of claim 12 , wherein the operations comprise: defining a partition of the second portion of the set of memory components based on the second partition closing time; and associating the partition of the second portion with a bin.
14 . The system of claim 1 , wherein the memory reliability values represent a quantity of program-erase (PE) cycles (PECs) or an age of the memory sub-system.
15 . The system of claim 1 , wherein the individual portion includes a superblock comprising a plurality of memory blocks across a plurality of memory dies.
16 . The system of claim 1 , wherein the memory sub-system comprises a three-dimensional (3D) NAND storage device.
17 . The system of claim 1 , wherein the operations comprise: searching the data to identify a range of memory reliability values corresponding to the individual portion of the set of memory components.
18 . The system of claim 17 , wherein the operations comprise: retrieving the partition closing time from the data associated with the range of memory reliability values.
19 . A method comprising: storing data that associates different ranges of memory reliability values with different partition closing times; selecting, based on the stored data, a partition closing time for an individual portion of a set of memory components; and defining a partition of the individual portion of the set of memory components based on the partition closing time.
20 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: storing data that associates different ranges of memory reliability values with different partition closing times; selecting, based on the data, a partition closing time for an individual portion of a set of memory components; and defining a partition of the individual portion of the set of memory components based on the partition closing time.

Description

PRIORITY APPLICATION This application is a continuation of U.S. application Ser. No. 17/892,581, filed Aug. 22, 2022, which is incorporated herein by reference in its entirety. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems and, more specifically, to performing adaptive memory read level threshold operations in a memory sub-system. BACKGROUND A memory sub-system can be a storage system, such as a solid-state drive (SSD), and can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory sub-system to store data at the memory components and to retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 is a block diagram illustrating an example computing environment including a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 2 is a block diagram of an example read level threshold module, in accordance with some implementations of the present disclosure. FIG. 3 is a block diagram of an example closing timetable, in accordance with some implementations of the present disclosure. FIG. 4 is a block diagram of an example scan frequency table, in accordance with some implementations of the present disclosure. FIG. 5 is a flow diagram of an example method to perform adaptive read level threshold voltage operations, in accordance with some implementations of the present disclosure. FIG. 6 is a block diagram illustrating a diagrammatic representation of a machine in the form of a computer system within which a set of instructions can be executed for causing the machine to perform any one or more of the methodologies discussed herein, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to performing adaptive read level threshold voltage operations for a memory sub-system. The memory sub-system controller can tailor when partitions of different portions of a set of memory components are closed based on memory reliability values of the portions, such as a quantity of program-erase (PE) cycles of the portions and/or an age of the portions. The partitions can be associated with different bins, each of which represents an individual read level threshold voltage against which charge distribution of data stored in the portion is compared to determine one or more logical values. In this way, the duration of time that data can be written to a portion of the set of memory components before the bin (e.g., representing read level threshold voltage) associated with the portion is updated is controlled on the basis of the memory reliability value of the portion. This can reduce the number of PE cycles that are performed for the portion and improve the efficiency at which data is stored which improves the overall efficiency of operating the memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more memory components, such as memory devices that store data. The host system can send access requests (e.g., write command, read command, sequential write command, sequential read command) to the memory sub-system, such as to store data at the memory sub-system and to read data from the memory sub-system. The data specified by the host is hereinafter referred to as “host data” or “user data”. A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data and a particular zone in which to store or access the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., ECC codeword, parity code), data version (e.g., used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data), etc. The memory sub-system can initiate media management operations, such as a write operation, on host data that is stored on a memory device. For example, firmware of the memory sub-system may re-write previously written host data from a location on a memory device to a new location as part of garbage collection management operations. The data that is re-written, for example as initiated by the firmware, is hereinafter referred to as “garbage collection data”. “User data” can include host data and gar