US-12625641-B2 - Memory controller and method of operating the same

Abstract

Provided herein are a memory controller and a method of operating the same. The memory controller may include a background condition storage and a background controller. The background condition storage may be configured to store a trigger condition for each background operation for a memory device in each of a non-charging mode and a charging mode associated with a battery for the memory controller. The background controller may be configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state. The trigger condition is mitigated in the charging condition compared to the non-charging condition.

Inventors

• In Jong Jang

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20240227

Priority Date

20230724

Claims (18)

1. 1 . A memory controller comprising: a background condition storage configured to store a trigger condition for each background operation for a memory device; and a background controller configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state, wherein the trigger condition is mitigated in the charging condition compared to the non-charging condition, and wherein the background operation consumes more power or has a higher execution frequency in the charging condition than that in the non-charging condition.
2. 2 . The memory controller according to claim 1 , wherein the background controller is configured to receive the charging information from a host, set the trigger condition to the charging condition in response to charging information indicating that the battery is in the charging state, and set the trigger condition to the non-charging condition in response to charging information indicating that the battery is in a non-charging state.
3. 3 . The memory controller according to claim 2 , wherein: the background controller is configured to control each background operation of the memory device based on the set trigger condition.
4. 4 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a dirty level for triggering garbage collection among background operations, and the dirty level indicates a necessity for a free block of the memory device to be secured through the garbage collection and is less in the charging condition than in the non-charging condition.
5. 5 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a reference invalid page count based on which corresponding memory block of the memory device is selected as a victim block on which garbage collection among background operations is to be performed, and the reference invalid page count is less in the charging condition than in the non-charging condition.
6. 6 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a reference read count for triggering a read reclaim operation among background operations, and the reference read count is less in the charging condition than in the non-charging condition.
7. 7 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a reference number of error bits for a test read of the memory device based on which block of the memory device is selected on which a read reclaim operation among background operations is to be performed, and the reference number of error bits is less in the charging condition than in the non-charging condition.
8. 8 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a reference interval for a test read of the memory device based on which block of the memory device is selected on which a read reclaim operation among background operations is to be performed, and the reference interval for the test read is shorter in the charging condition than in the non-charging condition.
9. 9 . The memory controller according to claim 8 , wherein the test read is performed on a page programmed last among pages included in a memory block of the memory device.
10. 10 . The memory controller according to claim 1 , wherein: the background condition storage is configured to store, as the trigger condition, a condition regarding a reference erase or write count on which block of the memory device is selected on which wear leveling among background operations is to be performed, and the reference erase or write count is less in the charging condition than in the non-charging condition.
11. 11 . A method of operating a memory controller, the method comprising: receiving, from a host, charging information indicating whether a battery for the memory controller is in a charging state; changing a trigger condition for a background operation for a memory device to a charging condition that is mitigated compared to a non-charging condition based on the charging information; and performing the background operation on the memory device based on the trigger condition, wherein the background operation consumes more power or has a higher execution frequency, as the trigger condition, in the charging condition than in the non-charging condition.
12. 12 . The method according to claim 11 , further comprising: receiving from the host charging information indicating that the battery is in a non-charging state; and changing the trigger condition for the background operation from the charging condition to the non-charging condition.
13. 13 . The method according to claim 11 , wherein: performing the background operation comprises performing garbage collection based on the trigger condition of a dirty level, less than that in the non-charging condition, and the dirty level indicates a necessity for a free block of the memory device to be secured through the garbage collection.
14. 14 . The method according to claim 11 , wherein performing the background operation comprises: selecting a target block of the memory device on which a read reclaim operation is to be performed based on the trigger condition of a read count less than that in the non-charging condition; and performing the read reclaim operation on the target block.
15. 15 . The method according to claim 11 , wherein performing the background operation comprises: selecting a target block of the memory device on which a read reclaim operation is to be performed based on the trigger condition of a number of error bits less than that in the non-charging condition; and performing the read reclaim operation on the target block.
16. 16 . The method according to claim 11 , wherein performing the background operation comprises: performing a test read of the memory device at an interval shorter than that in the non-charging condition; and performing a read reclaim operation on a selected target block of the memory device depending on a result of the test read.
17. 17 . The memory controller according to claim 16 , wherein the test read is performed on a page programmed last among pages included in a memory block of the memory device.
18. 18 . The method according to claim 11 , wherein performing the background operation comprises: selecting a target block of the memory device on which wear leveling is to be performed based on the trigger condition of an erase or write count less than that in the non-charging condition; and performing the wear leveling on the target block.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2023-0096047 filed on Jul. 24, 2023, the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Field of Invention Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a memory controller and a method of operating the memory controller. 2. Description of Related Art A storage device is a device which stores data under the control of a host device, such as a computer or a smartphone. A storage device may include a memory device in which data is stored and a memory controller which controls the memory device. Such memory devices are classified into a volatile memory device and a nonvolatile memory device. The memory controller may perform background operations on the memory device to improve the reliability of the memory device and increase the lifespan of the memory device. The background operations may include garbage collection, a read reclaim operation, wear leveling, etc. The memory controller may receive charging information from the host indicating whether a battery which supplies power to the storage device is in a charging state, and may change an execution condition for each background operation so that the corresponding background operation is performed by consuming more power depending on the charging information. SUMMARY Various embodiments of the present disclosure are directed to a storage device which performs background operations in a stabilized power state, and a method of operating the storage device. An embodiment of the present disclosure may provide for a memory controller. The memory controller may include a background condition storage and a background controller. The background condition storage may be configured to store a trigger condition for each background operation for a memory device in each of a non-charging mode and a charging mode associated with a battery for the memory controller. The background controller may be configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state. The trigger condition is mitigated in the charging condition compared to the non-charging condition. An embodiment of the present disclosure may provide for a method of operating a memory controller. The method may include receiving from a host charging information indicating whether a battery for the memory controller is in a charging state, changing a trigger condition for a background operation for a memory device to a charging condition that is mitigated compared to a non-charging condition, and performing the background operation on the memory device based on the trigger condition corresponding to the charging condition. These and other features and advantages of the invention will become apparent from the detailed description of embodiments of the present disclosure and the following figures. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure. FIG. 2 is a sequence diagram illustrating a process of changing a trigger condition for a background operation according to an embodiment of the present disclosure. FIG. 3 is a flowchart illustrating the operation of a memory controller according to an embodiment of the present disclosure. FIG. 4 is a flowchart illustrating the operation of a memory controller according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating a background condition storage in which conditions regarding garbage collection are stored according to an embodiment of the present disclosure. FIG. 6A is a diagram illustrating garbage collection among background operations. FIG. 6B is a diagram illustrating a dirty level that is a trigger condition for garbage collection. FIG. 7 is a diagram illustrating a background condition storage in which conditions regarding a read reclaim operation are stored according to an embodiment of the present disclosure. FIG. 8A is a diagram illustrating a read reclaim operation among background operations and a read count that is a trigger condition for the read reclaim operation. FIG. 8B is a diagram illustrating the number of error bits that is a trigger condition for a read reclaim operation. FIG. 8C is a diagram illustrating a test read interval in a read reclaim operation. FIG. 9 is a diagram illustrating a background condition storage in which conditions regarding wear leveling are stored according to an embodiment of the present disclosure. FIG. 10 is a diagram illustrating wear leveling among background operations and an erase/write count that is a trigger condition for wear leveling. FIG. 11 is a diagram illustrating an embodiment of a memory controller of FIG. 1. DET