US-12625643-B2 - Sampling-based read enabling window generation method

US12625643B2US 12625643 B2US12625643 B2US 12625643B2US-12625643-B2

Abstract

Systems and methods are herein disclosed that relate to generating read enabling windows in a multi-rank memory system that includes a memory controller connected to a plurality of memory ranks via a shared physical channel. The systems and methods disclosed herein provide for opening and closing read enabling windows for a memory controller in response to processing of data strobe signals output by a memory rank connected to the memory controller. By processing of the data strobe signals, a preamble can be detected that precedes a data transmission from a memory rank to the memory controller and a post-amble that follows the data transmission can also be detected. Detection of the preamble triggers opening of the read enabling window, and detection of the post-amble triggers closing of the read enabling window.

Inventors

Jiwang LEE
Jaewon Lee
Po-Chien Chiang
Hsuche Nee
Wen-Hung Lo
Michael I. Halfen
Abhishek Dhir
Zhonghua Li

Assignees

NVIDIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240815

Claims (18)

1 . A read-enabling window generation module for a memory controller of a multi-rank memory system, the read-enabling window generation module being configured to trigger the generation of a read enabling window, the read-enabling window generation module comprising: processing circuitry configured to: detect, from a data strobe signal received from a respective memory rank of the multi-rank memory system, a read cycle preamble that precedes a transmission of data from the respective memory rank to the memory controller during a read cycle, output, in response to detecting the read cycle preamble, a trigger for opening the read enabling window, detect, from the data strobe signal received from the respective memory rank, a read cycle post-amble that follows the transmission of data from the respective memory rank to the memory controller during the read cycle, and output, in response to detecting the read cycle post-amble, a trigger for closing the read enabling window, wherein the processing circuitry comprises a preamble detection circuit, the preamble detection circuit being configured to detect the read cycle preamble and utilize a termination to receive the data strobe signal, the termination being a power termination or a ground termination.
2 . The read-enabling window generation module according to claim 1 , the preamble detection circuit comprising: an input configured to receive the data strobe signal from the respective memory rank via a shared physical channel that connects a plurality of memory ranks of the multi-rank memory system to the memory controller, the termination, and a comparator circuit configured to: process the data strobe signal and a reference signal, and provide, at an output of the preamble detection circuit, a result of one or more operations for detecting the read cycle preamble.
3 . The read-enabling window generation module according to claim 2 , wherein the termination is an on-die termination of the memory controller.
4 . A memory controller for a multi-rank memory system, the memory controller comprising: the read-enabling window generation module according to claim 3 .
5 . The read-enabling window generation module according to claim 2 , wherein the processing circuitry further comprises a logic circuit configured to provide, as output, a result of one or more logical operations configured to detect the read cycle post-amble.
6 . The read-enabling window generation module according to claim 5 , wherein the processing circuitry further comprises a first flip flop, the first flip-flop comprising a clock input and an output, wherein the clock input of the first flip-flop is connected to the output of the preamble detection circuit, and wherein the output of the first flip-flop is configured to: output the trigger for opening the read enabling window in response to the output of the preamble detection circuit indicating that the read cycle preamble has been detected, and output the trigger for closing the read enabling window in response to the output of the logic circuit indicating that the read cycle post-amble has been detected.
7 . The read-enabling window generation module according to claim 6 , wherein the processing circuitry further comprises a second flip flop, the second flip-flop comprising an input connected to the output of the preamble detection circuit, a clock input connected, via a delay, to the output of the preamble detection circuit, and an output, and wherein the logic circuit comprises a first input connected to the output of the second flip flop, a second input connected, via a delay, to the output of the second flip flop, and an output connected to a reset of the first flip flop.
8 . The read-enabling window generation module according to claim 2 , wherein the multi-rank memory system is a dual data rate (DDR) memory system, the data strobe signal is a differential data strobe signal comprising a true component and a complement component, the termination is a power termination, and the comparator circuit comprises a comparator configured to compare a value of the true component to a value of the reference signal.
9 . The read-enabling window generation module according to claim 2 , wherein the multi-rank memory system is a low-power dual data rate (LPDDR) memory system, the data strobe signal is a differential data strobe signal comprising a true component and a complement component, the termination is a ground termination, and the comparator circuit comprises a comparator configured to compare a value of the complement component to a value of the reference signal.
10 . A memory controller for a multi-rank memory system, the memory controller comprising the read-enabling window generation module according to claim 1 .
11 . A multi-rank memory system, the multi-rank memory system comprising: a memory controller comprising the read-enabling window generation module according to claim 1 ; a plurality of memory ranks; and a shared physical channel connecting the memory controller to the plurality of memory ranks.
12 . A method for self-generating a read enabling window of a memory controller for a multi-rank memory system, the method comprising: receiving a data strobe signal from a respective memory rank of the multi-rank memory system; detecting, from the data strobe signal, a read cycle preamble that precedes a transmission of data from the respective memory rank to the memory controller during a read cycle, wherein the detecting the read cycle preamble comprises providing the data strobe signal to a preamble detection circuit configured to detect the read cycle preamble, wherein the preamble detection circuit is configured to utilize a termination to receive the data strobe signal, the termination being a power termination or a ground termination; opening, in response to detecting the read cycle preamble, the read enabling window; detecting, from the data strobe signal, a read cycle post-amble that follows the transmission of data from the respective memory rank to the memory controller during the read cycle; and closing, in response to detecting the read cycle post-amble, the read enabling window.
13 . The method according to claim 12 , wherein the preamble detection circuit is configured to perform, via a comparator circuit, one or more operations configured to detect the read cycle preamble.
14 . The method according to claim 13 , wherein the detecting the read cycle post-amble comprises performing, via a logic circuit, a logical operation configured to detect the read cycle post-amble.
15 . The method according to claim 13 , wherein the multi-rank memory system is a dual data rate (DDR) memory system, the data strobe signal is a differential data strobe signal comprising a true component and a complement component, the preamble detection circuit is configured to utilize the power termination to receive the data strobe signal, and the comparator circuit comprises a comparator configured to compare the true component received via the termination to a reference signal.
16 . The method according to claim 13 , wherein the multi-rank memory system is a low power dual data rate (LPDDR) memory system, the data strobe signal is a differential data strobe signal comprising a true component and a complement component, the preamble detection circuit is configured to utilize the ground termination to receive the data strobe signal, and the comparator circuit comprises a comparator configured to compare the complement component received via the termination to a reference signal.
17 . The method according to claim 12 , wherein the opening, in response to detecting the read cycle preamble, the read enabling window is performed in response to a trigger, output by a first flip-flop, and wherein the closing, in response to detecting the read cycle post-amble, the read enabling window is performed in response to a trigger, output by the first flip flop.
18 . The method according to claim 17 , wherein the first flip-flop comprises: a clock input connected to an output of the preamble detection circuit, a reset connected to an output of a logic circuit configured to perform a logical operation configured to detect the read cycle post-amble, and an output configured to output the trigger for opening the read-enabling window and to output the trigger for closing the read-enabling window.

Description

BACKGROUND Multi-rank memory systems utilize multiple ranks of memory modules (i.e. multiple memory dies or groups of dies) to improve performance and capacity. Multi-rank memory systems include a memory controller connected to the multiple ranks of memory modules through a shared physical channel. Multi-rank memory systems offer, when compared to single-rank systems, improved performance due to parallelism and reduced contention. With multiple ranks, the memory controller can access different ranks independently. Therefore, when one rank is busy refreshing or performing internal operations, the controller can access another rank. This helps in hiding latency, thereby improving overall throughput, and also reduces contention for memory access, thereby leading to better performance in multi-threaded applications or workloads. Furthermore, multi-rank configurations enable more efficient use of the memory bus because the controller can switch between ranks to maximize data transfer rates and minimize idle periods. However, limits on the ability to rapidly switch from one rank to another represent limits on the improved performance that can be achieved via the use of multi-rank memory systems. In read operation, for example, the memory controller issues a command to a particular rank, and the rank transmits a data signal (DQ) along with a strobe signal (DQS) synchronized with the data after a pre-defined number of clock cycles (corresponding to the read latency of the rank). However, due to variation between memory dies and physical channel configurations, there exists some variation in the actual timing with which a memory rank transmits the data and strobe signals in response to the read command. As a result of such variation, the memory controller must either (i) provide a larger time gap between read enabling windows (i.e. periods during which an internal gate on the memory controller side is open for the reception of data from a rank) or (ii) perform training of the window timing (i.e. tune the read enabling windows to the memory ranks). However, both options represent time loss from the system point of view, thereby limiting performance improvements. Such time loss can be particularly severe if periodic re-training is required to cover voltage/temperature variation. SUMMARY Embodiments of the present disclosure relate to systems and methods for self-generating read enabling windows for a memory controller in multi-rank memory systems. According to an embodiment, a read-enabling window generation module for a memory controller of a multi-rank memory system is provided. The read-enabling window generation module is configured to trigger the generation of a read enabling window. The read-enabling window generation module includes processing circuitry configured to (i) detect, from a data strobe signal received from a respective memory rank of the multi-rank memory system, a read cycle preamble that precedes a transmission of data from the respective memory rank to the memory controller during a read cycle, (ii) output, in response to detecting the read cycle preamble, a trigger for opening the read enabling window, (iii) detect, from the data strobe signal received from the respective memory rank, a read cycle post-amble that follows the transmission of data from the respective memory rank to the memory controller during the read cycle, and (iv) output, in response to detecting the read cycle post-amble, a trigger for closing the read enabling window. According to an embodiment, a memory controller for a multi-rank memory system is provided. The memory controller includes a read-enabling window generation module configured to trigger the generation of a read enabling window. The read-enabling window generation module includes processing circuitry configured to (i) detect, from a data strobe signal received from a respective memory rank of the multi-rank memory system, a read cycle preamble that precedes a transmission of data from the respective memory rank to the memory controller during a read cycle, (ii) output, in response to detecting the read cycle preamble, a trigger for opening the read enabling window, (iii) detect, from the data strobe signal received from the respective memory rank, a read cycle post-amble that follows the transmission of data from the respective memory rank to the memory controller during the read cycle, and (iv) output, in response to detecting the read cycle post-amble, a trigger for closing the read enabling window. According to an embodiment, a multi-rank memory system is provided. The multi-rank memory system includes a memory controller comprising a read-enabling window generation module configured to trigger the generation of a read enabling window, a plurality of memory ranks, and a shared physical channel connecting the memory controller to the plurality of memory ranks. The read-enabling window generation module includes processing circuitry configured to (i) detect, fr