US-12625645-B2 - Memory device, memory system, and operating method of compression using position values

Abstract

A memory device includes first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values less than or equal to a first reference number, on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation.

Inventors

• JAEHUN JANG
• Sumin KIM
• Jiwon SEO
• Mankeun SEO
• Hongrak Son
• Dongmin Shin

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20240424

Priority Date

20230530

Claims (20)

1. 1 . A memory device comprising: first and second memory cell arrays, each including a plurality of memory cells; a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array; and a compression circuit configured to perform, for each of a plurality of partial segments included in one of the plurality of sub-segments, a first compression operation of generating a first compression segment including a number of position values, which are less than or equal to a first reference number, among position values representing a position of a bit having a first value in one of the plurality of sub-segments, and sequentially perform a plurality of compression operations, which are subsequent to the first compression operation, of generating, in each of the plurality of compression operations, a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each of the plurality of compression operations, of position values included in two or more previous compression segments.
2. 2 . The memory device of claim 1 , further comprising: an interface circuit configured to provide a memory controller with a next compression segment generated in a last compression operation of the plurality of compression operations.
3. 3 . The memory device of claim 1 , wherein the compression circuit is configured to, if the number of position values of bits having the first value included in a partial segment of the plurality of partial segments is less than the first reference number, add a dummy value to the first compression segment in the first compression operation and, if the number of position values included in two or more previous compression segments is less than a corresponding reference number, add the dummy value to a next compression segment in each of the plurality of compression operations.
4. 4 . The memory device of claim 1 , wherein a size of each of the plurality of sub-segments is 2 N (where N is a natural number) bits, wherein each of the position values is represented by using N+1 bits, wherein a size of the first compression segment corresponds to a multiplication of the first reference number by N+1 bits, and wherein in each of the plurality of compression operations, a size of the next compression segment corresponds to a multiplication of a corresponding reference number by N+1 bits.
5. 5 . The memory device of claim 1 , wherein the number of bits having the first value included in the one of the plurality of sub-segments is greater than the number of position values included in a next compression segment generated in a last compression operation of the plurality of compression operations.
6. 6 . The memory device of claim 1 , wherein the compression circuit comprises: a first sub compression circuit configured to, for each of the plurality of partial segments, obtain the position values representing positions of bits, having the first value, in one of the plurality of sub-segments in the first compression operation and select position values which are to be added to the first compression segment, based on sizes of the position values that were obtained; and a plurality of sub compression circuits configured to each perform a plurality of compression operations of receiving a plurality of previous compression segments and selecting position values which are to be added to a next compression segment, based on sizes of position values included in two or more previous compression segments, in each of the plurality of compression operations.
7. 7 . The memory device of claim 1 , wherein the compression circuit is configured to perform at least one of the first compression operation and the plurality of compression operations while hard decision data read from the second memory cell array is being output.
8. 8 . The memory device of claim 1 , wherein bits having the first value are soft decision data bits for memory cells, having a threshold voltage between two or more soft read voltage levels applied to a word line, of memory cells included in the first memory cell array.
9. 9 . The memory device of claim 1 , wherein the compression circuit is configured to generate the first compression segment and a next compression segment in each of the plurality of compression operations, based on a position mapping table representing position values of bits included in the one of the plurality of sub-segments.
10. 10 . An operating method of a memory device, the operating method comprising: reading soft decision data including a plurality of sub-segments from a first memory cell array; obtaining, for each of a plurality of partial segments included in one of the plurality of sub-segments, position values representing a position of a bit having a first value in one of the plurality of sub-segments; performing, for each of the plurality of partial segments, a first compression operation of generating a first compression segment which has a first size, selectively includes a dummy value, and includes a number of position values, which is less than or equal to a first reference number, of corresponding position values; sequentially performing a plurality of compression operations subsequent to the first compression operation, by, in the each of the plurality of compression operations, combining position values included in two or more previous compression segments to generate a next compression segment, having a size corresponding to each compression operation and including a number of position values which are less than or equal to a reference number corresponding to each of the plurality of compression operations; and providing a memory controller with a compression segment generated in a last compression operation of the plurality of compression operations.
11. 11 . The operating method of claim 10 , wherein the performing of the first compression operation comprises combining a number of dummy values corresponding to a difference between the first reference number and the number of bits having the first value to the first compression segment, and wherein the sequentially performing of the plurality of compression operations comprises in each of the plurality of compression operations, combining a number of dummy values corresponding to a difference between a reference number corresponding to each compression operation and the number of position values included in two or more previous compression segments to the next compression segment.
12. 12 . The operating method of claim 10 , wherein a size of each of the plurality of sub-segments is 2 N (where N is a natural number) bits, wherein each of the position values is represented by using N+1 bits, wherein a size of the first compression segment corresponds to a multiplication of the first reference number by N+1 bits, and wherein in each of the plurality of compression operations, a size of a next compression segment corresponds to a multiplication of a corresponding reference number by N+1 bits.
13. 13 . The operating method of claim 10 , wherein the number of bits having the first value included in the one of the plurality of sub-segments is greater than the number of position values included in a next compression segment generated in a last compression operation of the plurality of compression operations.
14. 14 . The operating method of claim 10 , wherein the performing of the first compression operation comprises: obtaining, for each of the plurality of partial segments, the position values representing positions of bits having the first value in one of the plurality of sub-segments; and selecting position values which are to be added to the first compression segment, based on sizes of the position values that were obtained.
15. 15 . The operating method of claim 10 , wherein the performing of the first compression operation or the performing of the plurality of compression operations is performed while hard decision data read from a second memory cell array is provided to the memory controller.
16. 16 . A memory system comprising: a memory device configured to read hard decision data and soft decision data including a plurality of sub-segments from a memory cell array, perform, for each of a plurality of partial segments included in one of the plurality of sub-segments, a first compression operation of generating a first compression segment including a number of position values, which are less than or equal to a first reference number, among position values representing a position of a bit having a first value in one of the plurality of sub-segments, and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating, in each of the plurality of compression operations, a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each of the plurality of compression operations, of position values included in two or more previous compression segments; and a memory controller configured to receive a second compression segment generated by a last compression operation of the plurality of compression operations and obtain a decompression sub-segment corresponding to the one of the plurality of sub-segments, based on position values included in the second compression segment.
17. 17 . The memory system of claim 16 , wherein the memory device is configured to, in the first compression operation, if the number of position values of bits having the first value included in one of the plurality of partial segments is less than the first reference number, add a dummy value to the first compression segment and, in each of the plurality of compression operations, if the number of position values included in two or more previous compression segments is less than a corresponding reference number, add the dummy value to the next compression segment.
18. 18 . The memory system of claim 16 , wherein the memory controller is configured to generate the decompression sub-segment having bits corresponding to a size of the one of the plurality of sub-segments so that a first bit indicated by each of position values included in the second compression segment has the first value, and a second bit has a second value.
19. 19 . The memory system of claim 18 , wherein the memory controller comprises: a plurality of conversion circuits configured to respectively receive different position values included in the second compression segment, convert a bit, represented by a received position value among bits corresponding to a size of the one of the plurality of sub-segments, into the first value, and convert the second bit into a second value, thereby outputting a partial decompression sub-segment; and an OR gate configured to receive a different plurality of partial decompression sub-segments from the plurality of conversion circuits and perform an OR operation on the different plurality of partial decompression sub-segments to generate the decompression sub-segment.
20. 20 . The memory system of claim 16 , wherein the number of bits having the first value included in the one of the plurality of sub-segments is greater than the number of bits having the first value included in the decompression sub-segment.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2023-0069457, filed on May 30, 2023, and 10-2023-0114258, filed on Aug. 30, 2023, in the Korean Intellectual Property Office, the disclosure of which are incorporated by reference herein in their entirety. BACKGROUND The inventive concept relates to a memory device, and more particularly, to a memory device for compressing soft decision data and an operating method of the memory device. Non-volatile memory devices may read hard decision data based on a hard read voltage and may generate soft decision data by using read values read based on a plurality of soft read voltages. The soft decision data may be information representing the reliability of the hard decision data. A memory controller may perform an error correction operation based on the hard decision data and the soft decision data. SUMMARY The inventive concept relates to a memory device which performs fixed size compression on soft decision data and provides a memory device and an operating method thereof, which encodes the position of a minor bit included in soft decision data to generate compressed data. According to some embodiments of the inventive concept, there is provided a memory device including first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values, which are less than or equal to a first reference number, among position values representing a position of a bit having a first value on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation. According to some embodiments of the inventive concept, there is provided an operating method of a memory device, the operating method including reading soft decision data included in a plurality of sub-segments from a first memory cell array, obtaining position values representing a position of a bit having a first value on each of a plurality of partial segments included in one sub-segment among the plurality of sub-segments, performing a compression operation of generating a first compression segment which has a first size, selectively includes a dummy value, and includes a number of position values, which is less than or equal to a first reference number, of corresponding position values, on each of the plurality of partial segments, combining position values included in two or more previous compression segments to generate a next compression segment, having a size corresponding to each compression operation and including a number of position values which are less than or equal to a reference number corresponding to each compression operation, and sequentially performing a plurality of compression operations subsequent to the first compression operation, and providing a memory controller with a compression segment generated in a last compression operation of the plurality of compression operations. According to some embodiments of the inventive concept, there is provided a memory system including a memory device configured to read hard decision data and soft decision data including a plurality of sub-segments from a memory cell array, perform a first compression operation of generating a first compression segment including a number of position values, which are less than or equal to a first reference number, among position values representing a position of a bit having a first value on each of a plurality of partial segments included in one of the plurality of sub-segments, and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation and a memory controller configured to receive a second compression segment generated by a last compression operation of the plurality of compression operations and obtain a decompression sub-segment corresponding to the one of the plurality of sub-segments, based on position values included in the second compression segment. BRIEF DESCRIPTION OF THE DRAWIN