US-12625648-B2 - Activate information on preceding precharge command

Abstract

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Inventors

• Kwang-Ho Cho

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240725

Claims (20)

1. 1 . A system comprising: a first circuit comprising: one or more D latches, clocked by a signal generated based on a preceding command, configured to receive one or more command/address (CA) signals included in the preceding command, wherein the one or more CA signals indicate a first portion of activate information for a memory bank; and a second circuit configured to: receive a second portion of the activate information for the memory bank from an activate command subsequent to the preceding command, wherein the memory bank is activated by the activate command using the first portion of the activate information and the second portion of the activate information.
2. 2 . The system of claim 1 , wherein the preceding command comprises a precharge command.
3. 3 . The system of claim 1 , wherein the preceding command comprises a column command.
4. 4 . The system of claim 1 , wherein the preceding command comprises an unused valid bit and the first portion of the activate information is transmitted by using the unused valid bit.
5. 5 . The system of claim 1 , wherein the first portion of the activate information is different from the second portion of the activate information.
6. 6 . The system of claim 1 , wherein the first portion of the activate information comprises a row address term.
7. 7 . The system of claim 1 , wherein the second portion of the activate information comprises a bank address term associated with an address of the memory bank.
8. 8 . The system of claim 1 , wherein the first circuit is configured to receive a set of activate information for a plurality of memory banks using respective D latches.
9. 9 . The system of claim 8 , wherein the first circuit comprises a selection device to select the first portion of the activate information from the set of activate information for the plurality of memory banks based on a select signal generated based on the second portion of the activate information.
10. 10 . The system of claim 1 , wherein a clock signal is used to receive the first portion of the activate information and the second portion of the activate information, wherein the clock signal is generated based on the activate command.
11. 11 . A device, comprising: a memory bank; and command decoder circuitry comprising one or more D latches clocked by a signal generated based on a command received at a first clock cycle, wherein the one or more D latches are configured to receive one or more command/address (CA) signals included in the command, wherein the one or more CA signals indicate a first portion of activate information regarding the memory bank, wherein the command decoder circuitry is configured to: receive an activate command for activating the memory bank at a second clock cycle, wherein the activate command comprises a second portion of the activate information regarding the memory bank; and activate the memory bank using the first portion and the second portion of the activate information at the second clock cycle.
12. 12 . The device of claim 11 , wherein the command comprises a precharge command.
13. 13 . The device of claim 11 , wherein the command comprises a column command.
14. 14 . The device of claim 11 , wherein the command comprises an unused valid bit and the first portion of the activate information is transmitted by using the unused valid bit.
15. 15 . The device of claim 11 , wherein the first portion of the activate information is different from the second portion of the activate information.
16. 16 . A method comprising: receiving, via one or more D latches clocked by a signal generated based on a command received at a first clock cycle, wherein the one or more D latches are configured to receive one or more command/address (CA) signals included in the command, wherein the one or more CA signals indicate a first portion of activate information regarding a memory bank; receiving an activate command for activating the memory bank at a second clock cycle, wherein the activate command comprises a second portion of the activate information regarding the memory bank; and activating the memory bank using the first portion and the second portion of the activate information regarding the memory bank at the second clock cycle.
17. 17 . The method of claim 16 , wherein the command comprises a precharge command.
18. 18 . The method of claim 16 , wherein the command comprises a column command.
19. 19 . The method of claim 16 , comprising: receiving the first portion of the activate information using an unused valid bit in the command.
20. 20 . The method of claim 16 , wherein the first portion of the activate information is different from the second portion of the activate information.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/633,351, filed Apr. 12, 2024, which is incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION Field Of The Invention The present invention relates generally to the field of memory devices. More specifically, embodiments of the present disclosure relate to providing memory commands for accessing, sensing, and other operations for memory cells. Description Of The Related Art Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal memory, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random-access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others, may require a source of applied power to maintain its data. Non-volatile memory, by contrast, may retain its stored data even when not externally powered. Non-volatile memory is available in a wide variety of technologies, including flash memory (e.g., NAND and NOR) phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others. A memory device may include a number of storage elements, such as memory cells. Memory cells of a binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor of a memory cell may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous. Some of the memory devices include memory cells that may be accessed by turning on a transistor that couples the memory cell (e.g., the capacitor) with a wordline or a bitline/digit line. Different memory devices may use different architectures for arranging the memory cells. For example, different memory devices may arrange the memory cells in 2-dimensional or 3-dimensional rows and columns. A memory cell may be accessed based on activating a row and a column of the memory device corresponding to the memory cell. Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Emerging memory technologies may require greater activation power. To reduce power associated with activation, page sizes may be decreased, which may result in greater row address terms and less column terms. Further, increased density may require more row address terms. Moreover, to provide flexibility to controllers in memory devices, a dynamic page size activation feature may be provided allowing multiple page sizes (e.g., 64 B or 128 B) to be activated, which may require extra activate information. Additional row address and dynamic page size information may be transmitted with the activate (ACT) command, but the available DRAM ACT command address tables (e.g., generated for 7-pin command/address interface) may not accommodate transmission of the additional activate information. Additional command/address (CA) bus pins may be used to transmit additional activate information to the memory device, however, the physical compatibility may be reduced. The number of clock cycles that constitute an ACT command may also be increased to transmit additional activate information to the memory device, however, the system performance may be reduced. Further, the transmission of additional activate information on a subsequent column command may require additional circuit area and heavily modified specifications. Accordingly, it is desirable to allow additional activate information to be transmitted to the memory device without requiring additional command/address (CA) bus pins, increasing activate cycle count, or impacting die size. BRIEF DESCRIPTION OF THE DRAWINGS Various aspects of this disclosure may better be understood upon reading the following detailed description and upon reference to the drawings in which: FIG. 1 is a block diagram illustrating certain features of a memory device, according to an embodiment of the present disclosure; FIG. 2 illustrates a memory bank of the memory device of FIG. 1, according to an embodiment of the present disclosure; FIG. 3A is a truth table for column commands for a memory device, according to an