US-12625676-B2 - Memory device and operating method thereof

Abstract

A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

Inventors

• Wei-Chen Wang
• Han-Wen Hu
• Yung-Chun Li
• Huai-Mu WANG
• Chien-Chung Ho
• Yuan-Hao Chang
• Tei-Wei Kuo

Assignees

• MACRONIX INTERNATIONAL CO., LTD.

Dates

Publication Date

20260512

Application Date

20220602

Claims (15)

1. 1 . A memory device, comprising: a memory array, for storing a plurality of vector data, each vector data has an MSB vector and a LSB vector, and the memory array comprises: a plurality of memory units, each memory unit has a first bit and a second bit, the first bit is used to store the MSB vector of each vector data, and the second bit is used to store the LSB vector of each vector data; and a counting circuit, comprising a plurality of logic circuits and an accumulator and used for executing a first group-counting operation according to a first data amount and executing a second group-counting operation according to a second data amount based on a majority function, wherein, each vector data is processed with a multiplying-operation, the MSB vector of each vector data is processed with the first group-counting operation, the LSB vector of each vector data is processed with the second group-counting operation, and the threshold voltage distribution of each memory unit is divided into N states, N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
2. 2 . The memory device according to claim 1 , wherein a physical page of the memory array has a plurality of logic pages, the logic pages include a high page and a low page, the high page corresponds to the first bit to store the MSB vector, the low page corresponds to the second bit to store the LSB vector.
3. 3 . The memory device according to claim 1 , wherein the vector data include a plurality of weight feature vectors and an input feature vector, the memory array stores the weight feature vectors and receives the input feature vector, and executes the multiplying-operation according to the input feature vector and one of the weight feature vectors.
4. 4 . The memory device according to claim 3 , wherein the counting circuit executes an accumulating-operation according to a result of the multiplying-operation and executes the first group-counting operation for the MSB vector of the input feature vector and the weight feature vectors.
5. 5 . The memory device according to claim 4 , wherein the counting circuit executes the second group-counting operation for the LSB vector of the input feature vector and the weight feature vectors, and the second group-counting operation is executed according to a second data amount, the bit number of the second data amount is greater than the bit number of the first data amount.
6. 6 . The memory device according to claim 5 , wherein the memory array reads the MSB vector and the LSB vector of the weight feature vectors according to a selective bit line read operation; wherein, the selective bit line read operation for the MSB vector of the weight feature vectors is executed concurrently with the second group-counting operation for the LSB vector of the weight feature vectors.
7. 7 . The memory device according to claim 6 , wherein a bit-line-setup for the selective bit line read operation is executed concurrently with the first group-counting operation for the MSB vector of the weight feature vectors.
8. 8 . An operating method of a memory device, wherein the memory device includes a memory array, the memory array includes a plurality of memory units, each memory unit has a first bit and a second bit, the operating method comprising: storing a plurality of vector data in the memory array, each vector data has an MSB vector and a LSB vector; storing the MSB vector of each vector data in the first bit; and storing the LSB vector of each vector data in the second bit; executing a multiplying-operation for each vector data; executing a first group-counting operation for the MSB vector of each vector data; and executing a second group-counting operation for the LSB vector of each vector data; wherein, a threshold voltage distribution of each memory unit is divided into N states, N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
9. 9 . The operating method according to claim 8 , wherein a physical page of the memory array has a plurality of logic pages, the logic pages include a high page and a low page, the high page corresponds to the first bit to store the MSB vector, the low page corresponds to the second bit to store the LSB vector.
10. 10 . The operating method according to claim 8 , wherein the vector data include a plurality of weight feature vectors and an input feature vector, the operating method further comprises: storing the weight feature vectors in the memory array; receiving the input feature vector, and executing the multiplying-operation according to the input feature vector and one of the weight feature vectors.
11. 11 . The operating method according to claim 10 , further comprising: executing an accumulating-operation according to a result of the multiplying-operation; wherein, the MSB vector of the input feature vector and the weight feature vectors is executed with the first group-counting operation to perform the accumulating-operation, and the first group-counting operation is executed according to a first data amount.
12. 12 . The operating method according to claim 11 , further comprising: executing the second group-counting operation for the LSB vector of the input feature vector and the weight feature vectors to perform the accumulating-operation, and the second group-counting operation is executed according to a second data amount, the bit number of the second data amount is greater than the bit number of the first data amount.
13. 13 . The operating method according to claim 12 , wherein the first group-counting operation and the second group-counting operation are executed selectively using a majority function.
14. 14 . The operating method according to claim 12 , further comprising: executing a selective bit line read operation to read the MSB vector and the LSB vector of the weight feature vectors; wherein, the selective bit line read operation for the MSB vector of the weight feature vectors is executed concurrently with the second group-counting operation for the LSB vector of the weight feature vectors.
15. 15 . The operating method according to claim 14 , wherein a bit-line-setup for the selective bit line read operation is executed concurrently with the first group-counting operation for the MSB vector of the weight feature vectors.

Description

This application claims the benefit of U.S. provisional application Ser. No. 63/298,614, filed Jan. 11, 2022, the subject matter of which is incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device and an operating method thereof, and more particularly, to a memory device and an in-memory computation method. BACKGROUND With the rapid development of artificial intelligence (AI) algorithms, researchers seek hardware devices suitable for executing AI algorithms. Semiconductor memory devices, such as NAND-type memory arrays, may perform AI computations through in-memory computation (IMC). When performing a multiply-and-accumulate (MAC) operation commonly used in AI, each memory unit of the memory array may output current to the bit line according to a result of multiplying-operation, and accumulate currents on the same bit line to generate a result of accumulating-operation. In a memory array, performing the MAC-operation in an analog manner may achieve a faster computation speed. However, overlaps of the current distribution may lead to misjudgment of the computation result, thereby reducing computation accuracy. Furthermore, when the computation data has a larger number of bits, accumulating the bits one by one will consume more computation resource and computation time. Moreover, performing several times of bit line setups will also consume several of setup-time and reduce computation speed. In addition, when the memory array uses multi-level cells (MLC) to store data, threshold voltage distribution of the memory units may have a larger number of states, which will lead to narrowing of the voltage intervals for the reading-voltage, and error in the reading-operation may be caused. In view of the above-mentioned technical problem, those skilled of the related industries in the technical field are devoted to improve storing mechanism of memory units and operating method of IMC, so as to enhance computation accuracy and computation speed. SUMMARY Technical solutions of the present disclosure provide executing digital MAC-operation by memory array, reducing the number of states of threshold voltage distribution of memory units and employing pipelined computation schedule and majority group-counting, so as to enhance computation accuracy and computation speed. According to an aspect of the present disclosure, a memory device is provided, the memory device comprises a memory array for storing a plurality of vector data, each vector data has an MSB vector and a LSB vector. The memory array comprises a plurality of memory units, each memory unit has a first bit and a second bit, the first bit is used to store the MSB vector of each vector data, and the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector of each vector data is executed with a first group-counting operation, the LSB vector of each vector data is executed with a second group-counting operation, and the threshold voltage distribution of each memory unit is divided into N states, N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2. According to another aspect of the present disclosure, an operating method of a memory device is provided, wherein the memory device includes a memory array, the memory array includes a plurality of memory units, each memory unit has a first bit and a second bit, the operating method comprises the following steps. Storing a plurality of vector data in the memory array, each vector data has an MSB vector and a LSB vector. Storing the MSB vector of each vector data in the first bit. Storing the LSB vector of each vector data in the second bit. Executing a multiplying-operation for each vector data. Executing a first group-counting operation for the MSB vector of each vector data. Executing a second group-counting operation for the LSB vector of each vector data. The threshold voltage distribution of each memory unit is divided into N states, N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a memory device according to an embodiment of the present disclosure. FIG. 1B is a flowchart of the MAC-operation performed by the memory device of the present disclosure. FIG. 1C is a schematic diagram illustrating states of threshold voltage distribution of a normal 2-bit MLC memory unit. FIG. 1D is a schematic diagram illustrating states of threshold voltage distribution of a 1.5-bit MLC memory unit according to an embodiment of the present disclosure. FIGS. 2A to 2E are schematic diagrams of various embodiments of counting-operations performed by the memory device of the present disclosure. FIG. 3 is a schematic diagram of an embodiment of a group-counting operation perfor