US-12625702-B2 - Real-time validation of microcode updates

Abstract

Real-time validation of microcode updates may include: executing a workload on at least one first processor having a first version of a microcode instruction set; executing the workload on at least one second processor having a second version of a microcode instruction set, wherein the second version of the microcode instruction set comprises an update of the first version of the microcode instruction set; and validating the second version of the microcode instruction set based on a comparison of output from executing the workload using the at least one first processor and output from executing the workload using the at least one second processor.

Inventors

• Michael E Gildein
• Tabari ALEXANDER

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20231207

Claims (20)

1. 1 . A method comprising: executing a workload on at least one first processor having a first version of a microcode instruction set; executing the workload on at least one second processor having a second version of a microcode instruction set, wherein the second version of the microcode instruction set comprises an update of the first version of the microcode instruction set; and validating the second version of the microcode instruction set based on a comparison of output from executing the workload using the at least one first processor and output from executing the workload using the at least one second processor.
2. 2 . The method of claim 1 , wherein executing the workload on the at least one first processor and executing the workload on the at least one second processor are performed substantially in parallel.
3. 3 . The method of claim 1 , further comprising causing the at least one first processor to be updated with the second version of the microcode instruction set in response to successfully validating the second version of the microcode instruction set.
4. 4 . The method of claim 1 , further comprising causing the at least one second processor to revert to the first version of the microcode instruction set in response to unsuccessfully validating the second version of the microcode instruction set.
5. 5 . The method of claim 4 , further comprising providing, to a remotely disposed computing device, data describing a failed validation of the second version of the microcode instruction set in response to unsuccessfully validating the second version of the microcode instruction set.
6. 6 . The method of claim 1 , wherein validating the second version of the microcode instruction set comprises determining whether one or more conditions have been satisfied indicating that validation is complete.
7. 7 . The method of claim 6 , wherein the one or more conditions comprise executing a full instruction set for the second version of the microcode instruction set.
8. 8 . The method of claim 6 , wherein the one or more conditions comprise passage of a predefined time duration without a failed validation.
9. 9 . The method of claim 6 , wherein the one or more conditions comprise execution of a particular instruction a predefined number of times without a failed validation.
10. 10 . The method of claim 1 , further comprising: selecting the at least one second processor from a plurality of processors; and updating the at least one second processor to implement the second version of the microcode instruction set.
11. 11 . An apparatus comprising: a processing device; and memory operatively coupled to the processing device, wherein the memory stores computer program instructions that, when executed, cause the processing device to: execute a workload on at least one first processor having a first version of a microcode instruction set; execute the workload on at least one second processor having a second version of a microcode instruction set, wherein the second version of the microcode instruction set comprises an update of the first version of the microcode instruction set; and validate the second version of the microcode instruction set based on a comparison of output from executing the workload using the at least one first processor and output from executing the workload using the at least one second processor.
12. 12 . The apparatus of claim 11 , wherein executing the workload on the at least one first processor and executing the workload on the at least one second processor are performed substantially in parallel.
13. 13 . The apparatus of claim 11 , wherein the instructions, when executed, further cause the processing device to cause the at least one first processor to be updated with the second version of the microcode instruction set in response to successfully validating the second version of the microcode instruction set.
14. 14 . The apparatus of claim 11 , wherein the instructions, when executed, further cause the processing device to cause the at least one second processor to revert to the first version of the microcode instruction set in response to unsuccessfully validating the second version of the microcode instruction set.
15. 15 . The apparatus of claim 14 , wherein the instructions, when executed, further cause the processing device to provide, to a remotely disposed computing device, data describing a failed validation of the second version of the microcode instruction set in response to unsuccessfully validating the second version of the microcode instruction set.
16. 16 . The apparatus of claim 11 , wherein validating the second version of the microcode instruction set comprises determining whether one or more conditions have been satisfied indicating that validation is complete.
17. 17 . The apparatus of claim 16 , wherein the one or more conditions comprise executing a full instruction set for the second version of the microcode instruction set.
18. 18 . The apparatus of claim 16 , wherein the one or more conditions comprise passage of a predefined time duration without a failed validation.
19. 19 . The apparatus of claim 16 , wherein the one or more conditions comprise execution of a particular instruction a predefined number of times without a failed validation.
20. 20 . A computer program product comprising a computer readable storage medium, wherein the computer readable storage medium comprises computer program instructions that, when executed: execute a workload on at least one first processor having a first version of a microcode instruction set; execute the workload on at least one second processor having a second version of a microcode instruction set, wherein the second version of the microcode instruction set comprises an update of the first version of the microcode instruction set; and validate the second version of the microcode instruction set based on a comparison of output from executing the workload using the at least one first processor and output from executing the workload using the at least one second processor.

Description

BACKGROUND The present disclosure relates to methods, apparatus, and products for real-time validation of microcode updates. SUMMARY According to embodiments of the present disclosure, various methods, apparatus and products for real-time validation of microcode updates are described herein. In some aspects, real-time validation of microcode updates includes executing a workload on at least one first processor having a first version of a microcode instruction set; executing the workload on at least one second processor having a second version of a microcode instruction set, wherein the second version of the microcode instruction set comprises an update of the first version of the microcode instruction set; and validating the second version of the microcode instruction set based on a comparison of output from executing the workload using the at least one first processor and output from executing the workload using the at least one second processor. In some aspects, an apparatus may include a processing device; and memory operatively coupled to the processing device, wherein the memory stores computer program instructions that, when executed, cause the processing device to perform this method. In some aspects, a computer program product comprising a computer readable storage medium may store computer program instructions that, when executed, perform this method. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 sets forth an example computing environment for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. FIG. 2 sets forth a flowchart of an example method for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. FIG. 3 sets forth a flowchart of another example method for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. FIG. 4 sets forth a flowchart of another example method for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. FIG. 5 sets forth a flowchart of another example method for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. FIG. 6 sets forth a flowchart of another example method for real-time validation of microcode updates in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION Certain processor architectures utilize a lower-level microcode instruction set that may be updated as part of a firmware update process. Though updates to a microcode instruction set are generally tested and validated prior to being pushed via a firmware update, certain errors may only be discovered when executed by a client using their particular production workflows. Accordingly, it may be beneficial to validate updates to microcode instruction sets using client-specific workloads. With reference now to FIG. 1, shown is an example computing environment according to aspects of the present disclosure. Computing environment 100 contains an example of an environment for the execution of at least some of the computer code involved in performing the various methods described herein, such as the validation module 107. In addition to block 107, computing environment 100 includes, for example, computer 101, wide area network (WAN) 102, end user device (EUD) 103, remote server 104, public cloud 105, and private cloud 106. In this embodiment, computer 101 includes processor set 110 (including processing circuitry 120 and cache 121), communication fabric 111, volatile memory 112, persistent storage 113 (including operating system 122 and block 107, as identified above), peripheral device set 114 (including user interface (UI) device set 123, storage 124, and Internet of Things (IoT) sensor set 125), and network module 115. Remote server 104 includes remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, host physical machine set 142, virtual machine set 143, and container set 144. Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer or any other form of computer or mobile device now known or to be developed in the future that is capable of running a program, accessing a network or querying a database, such as remote database 130. As is well understood in the art of computer technology, and depending upon the technology, performance of a computer-implemented method may be distributed among multiple computers and/or between multiple locations. On the other hand, in this presentation of computing environment 100, detailed discussion is focused on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 may be located in a cloud, even though it is not shown in a cloud in FIG. 1. On the other hand, computer 101 is not required to be in a clou