US-12625706-B2 - Instruction translation method and related device thereof

US12625706B2US 12625706 B2US12625706 B2US 12625706B2US-12625706-B2

Abstract

Embodiments of this application disclose an instruction translation method. The method includes: obtaining a return instruction of a function call instruction; obtaining a first address mapping result based on a second address indicated in the return instruction; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction, where the first translation result is a binary translation result of the return instruction, and the second translation result indicates to obtain, from a target location, an instruction indicated by the first address mapping result and execute the instruction. In this application, a running stack space of a source program is reused, thereby saving a storage space. In addition, an address of a return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation and increasing program running efficiency.

Inventors

Xianzhe Liu
JIANJIANG ZENG
Yandong LV

Assignees

HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240926
Priority Date: 20220331

Claims (20)

1 . An instruction translation method, comprising: obtaining a return instruction of a function call instruction to instruct to call an instruction indicated by a first address, and the return instruction is used to instruct to execute, after the instruction indicated by the first address is executed according to the function call instruction, an instruction indicated by a second address; obtaining a first address mapping result based on the second address, wherein the first address mapping result is a mapping result of the second address; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction based on the return instruction, wherein the first translation result is a translation result of the return instruction, and the first translation result indicates to obtain, from the running stack space, an instruction indicated by the first address mapping result and execute the instruction.
2 . The method according to claim 1 , wherein the storing the first address mapping result in the running stack space comprises: storing the first address mapping result at a target location in the running stack space, wherein the target location is a location corresponding to the second address in the running stack space.
3 . The method according to claim 1 wherein the second address is a source program counter (SPC), and the first address mapping result is a target program counter (TPC) of the second address.
4 . The method according to claim 1 , wherein after the storing the first address mapping result in the running stack space, the method further comprising: replacing the first address mapping result in the running stack space with the second address based on an access request for the second address.
5 . The method according to claim 1 , wherein after the storing the first address mapping result in the running stack space, the second address is modified, the method further comprising: obtaining a second address mapping result based on a modified second address, wherein the second address mapping result is a mapping result of the modified second address; and executing an instruction indicated by the second address mapping result, and skipping executing the first address mapping result.
6 . The method according to claim 5 , wherein the obtaining the second address mapping result of the second address based on the modified second address comprises: performing an address mapping on the modified second address, to obtain the second address mapping result.
7 . The method according to claim 1 , further comprising: obtaining a second translation result based on the function call instruction, wherein the second translation result is a translation result of the function call instruction.
8 . An apparatus for an instruction translation, comprising: a processor; and a memory coupled to the processor to store instructions, which when executed by the processor, cause the apparatus to: obtain a return instruction of a function call instruction to instruct to call an instruction indicated by a first address, and the return instruction is used to instruct to execute, after the instruction indicated by the first address is executed according to the function call instruction, an instruction indicated by a second address; obtain a first address mapping result based on the second address, wherein the first address mapping result is a mapping result of the second address; store the first address mapping result in a running stack space; and obtain a first translation result of the return instruction based on the return instruction, wherein the first translation result is a translation result of the return instruction, and the first translation result indicates to obtain, from the running stack space, an instruction indicated by the first address mapping result and execute the instruction.
9 . The apparatus according to claim 8 , wherein the apparatus is further caused to store the first address mapping result at a target location in the running stack space, wherein the target location is a location corresponding to the second address in the running stack space.
10 . The apparatus according to claim 8 , wherein the second address is a source program counter (SPC), and the first address mapping result is a target program counter (TPC) of the second address.
11 . The apparatus according to claim 8 , wherein the apparatus is further caused to: after the first address mapping result is stored in the running stack space, replace the first address mapping result in the running stack space with the second address based on an access request for the second address.
12 . The apparatus according to claim 8 , wherein after the first address mapping result is stored in the running stack space, the second address is modified, the apparatus is further caused to: obtain a second address mapping result based on a modified second address, wherein the second address mapping result is a mapping result of the modified second address; and execute an instruction indicated by the second address mapping result, and skip executing the first address mapping result.
13 . A non-transitory computer-readable storage medium having instructions stored therein, which when executed by a processor, cause the processor to perform obtaining a return instruction of a function call instruction to instruct to call an instruction indicated by a first address, and the return instruction is used to instruct to execute, after the instruction indicated by the first address is executed according to the function call instruction, an instruction indicated by a second address; obtaining a first address mapping result based on the second address, wherein the first address mapping result is a mapping result of the second address; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction based on the return instruction, wherein the first translation result is a translation result of the return instruction, and the first translation result indicates to obtain, from the running stack space, an instruction indicated by the first address mapping result and execute the instruction.
14 . A computing device, comprising: a processor; and a memory coupled to the processor to store instructions, which when executed by the processor, cause the processor to perform obtaining a return instruction of a function call instruction to instruct to call an instruction indicated by a first address, and the return instruction is used to instruct to execute, after the instruction indicated by the first address is executed according to the function call instruction, an instruction indicated by a second address; obtaining a first address mapping result based on the second address, wherein the first address mapping result is a mapping result of the second address; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction based on the return instruction, wherein the first translation result is a translation result of the return instruction, and the first translation result indicates to obtain, from the running stack space, an instruction indicated by the first address mapping result and execute the instruction.
15 . The non-transitory computer-readable storage medium according to claim 13 , wherein the storing the first address mapping result in the running stack space comprises: storing the first address mapping result at a target location in the running stack space, wherein the target location is a location corresponding to the second address in the running stack space.
16 . The non-transitory computer-readable storage medium according to claim 13 , wherein the second address is a source program counter (SPC), and the first address mapping result is a target program counter (TPC) of the second address.
17 . The non-transitory computer-readable storage medium according to claim 13 , wherein after the storing the first address mapping result in the running stack space, the instructions when executed by the processor, further cause the processor to perform: replacing the first address mapping result in the running stack space with the second address based on an access request for the second address.
18 . The computing device according to claim 14 , wherein the storing the first address mapping result in the running stack space comprises: storing the first address mapping result at a target location in the running stack space, wherein the target location is a location corresponding to the second address in the running stack space.
19 . The computing device according to claim 14 , wherein the second address is a source program counter (SPC), and the first address mapping result is a target program counter (TPC) of the second address.
20 . The computing device according to claim 14 , wherein after the storing the first address mapping result in the running stack space, the instructions when executed by the processor, further cause the processor to perform: replacing the first address mapping result in the running stack space with the second address based on an access request for the second address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2023/084280, filed on Mar. 28, 2023, which claims priority to Chinese Patent Application No. 202210346585.7, filed on Mar. 31, 2022. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD This application relates to the computer field, and in particular, to an instruction translation method and a related device thereof. BACKGROUND Binary translation (dynamic binary translation) is a technology for improving software portability and adaptability by modifying and monitoring software at a binary level during or before running. Dynamic binary translation is used as an example. Software using this technology is referred to as a dynamic binary translator (DBT). In a dynamic binary translation technology, dependency of software on hardware is avoided, so that source software runs on the dynamic binary translator instead of directly on hardware. In this way, the source software can run on a target machine. An indirect jump instruction is a type of jump instruction. Because a target address of the indirect jump instruction is known only during running, and the value may be different each time the indirect jump instruction is executed, a target program counter (TPC) corresponding to a source program counter (SPC) cannot be obtained when the indirect jump instruction is translated. To resolve this problem, a lookup table structure is introduced into the dynamic binary translator, and each source program counter and a corresponding target program counter are stored in the lookup table. When an indirect jump instruction is executed, an SPC is obtained from a register or a memory, and then a corresponding TPC is searched for by using the SPC as an index. In a typical application, a function return instruction is an indirect jump instruction. Because a same function may be called in a plurality of different places, during a function return, an indirect jump needs to be performed for returning the function to a place in which the function is called, for further execution. When dynamic binary translation is performed on the return instruction, if the lookup table structure needs to be accessed each time a function return is performed, context switch is frequently performed, causing a large performance loss. SUMMARY This application provides an instruction translation method. There is no need to use an independent data structure to store a mapping relationship between a source program counter and a target program counter of a return instruction, thereby saving a storage space. In addition, because a running stack space can sense a change of a return instruction, an address of the return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation. According to a first aspect, this application provides an instruction translation method. The method is applied to code translation, for example, may be applied to binary translation of code and other translation scenarios of code that needs to be compatible with different running conditions. For example, the method may be applied to dynamic binary translation, static binary translation, or a combination of dynamic and static binary translation of code. Dynamic binary translation may be understood as performing binary translation during running when an application is executed (that is, is run). In contrast, static binary translation may be binary translation performed offline, for example, binary translation performed before an application is run. The method includes: obtaining a return instruction of a function call instruction, where the function call instruction is used to instruct to call an instruction indicated by a first address, and the return instruction is used to instruct to execute, after the instruction indicated by the first address is executed according to the function call instruction, an instruction indicated by a second address: obtaining a first address mapping result based on the second address, where the first address mapping result is a mapping result of the second address: storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction based on the return instruction, where the first translation result is a translation result of the return instruction, and the first translation result indicates to obtain, from the running stack space, an instruction indicated by the first address mapping result and execute the instruction. In one embodiment, the second address is a source program counter SPC, and the first address mapping result is a target program counter TPC of the second address. In a current existing function return address optimization solution, an independent data structure is used to store a mapping relationship between an SPC and