US-12625723-B2 - Counters for ensuring transactional ordering in I/O agent

US12625723B2US 12625723 B2US12625723 B2US 12625723B2US-12625723-B2

Abstract

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

Inventors

Sagi Lahav
Lital Levy-Rubin
Gaurav Garg
Gerard R. Williams, III
Samer Nassar
Per H. Hammarlund
Harshavardhan Kaushikkar
Srinivasa Rangan Sridharan
Jeff Gonion

Assignees

APPLE INC.

Dates

Publication Date: 20260512
Application Date: 20220331

Claims (20)

1 . An apparatus, comprising: a memory controller circuit that is configured to couple to a memory and manage access to the memory; an input/output (I/O) agent circuit that includes a transaction pipeline and a pool of counters; and a first interconnect that is configured to couple the memory controller circuit and the I/O agent circuit; a second interconnect that is configured to couple the I/O agent circuit and one or more peripheral components; wherein the I/O agent circuit is configured to bridge the one or more peripheral components from the second interconnect to the first interconnect and implement coherency mechanisms for transactions associated with the one or more peripheral components, and wherein the I/O agent circuit is configured to: initialize a first counter included in the pool of counters with an initial counter value; assign the first counter to a specific transaction type; increment the first counter assigned to the specific transaction type in response to allocating a transaction of a particular, different transaction type than the specific transaction type; based on receiving a transaction request to process a first transaction of the specific transaction type, store pointer information to bind the first transaction to the first counter, wherein the first transaction is associated with a particular one of the one or more peripheral components; and issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.
2 . The apparatus of claim 1 , wherein the I/O agent circuit is further configured to: based on receiving the transaction request to process the first transaction, initialize a second counter and assign the second counter to the specific transaction type; and increment the second counter instead of the first counter as a part of allocating a transaction of the particular, different transaction type that is different than the specific transaction type.
3 . The apparatus of claim 1 , wherein the I/O agent circuit is further configured to: based on receipt of the transaction request to process the first transaction, increment one or more counters of the pool of counters based on the specific transaction type of the first transaction; and store, in association with the first transaction, one or more pointers that identify the one or more counters.
4 . The apparatus of claim 3 , wherein the I/O agent circuit is further configured to: based on a retirement of the first transaction, decrement the one or more counters identified by the one or more pointers associated with the first transaction.
5 . The apparatus of claim 1 , wherein the I/O agent circuit is further configured to: based on a retirement of the first transaction, release the first counter to the pool of counters such that the first counter is available to bind to another transaction.
6 . The apparatus of claim 1 , wherein the I/O agent circuit is further configured to: cease to increment the first counter while the first counter is bound to the first transaction.
7 . The apparatus of claim 1 , wherein the I/O agent circuit is further configured to: store transactions of a given one of a plurality of transaction types in a corresponding one of a plurality of queues, and wherein the I/O agent circuit is configured to issue the first transaction to the transaction pipeline based further on detecting that the first transaction is at a head of a queue associated with the first transaction.
8 . A method, comprising: initializing, by an input/output (I/O) agent circuit included in a computer system, a plurality of counters that respectively correspond to a plurality of different transaction types, wherein the I/O agent circuit includes a transaction pipeline and the plurality of counters, wherein the I/O agent circuit is configured to bridge one or more peripheral components coupled to a first interconnect to a second interconnect coupled to a memory controller circuit, and wherein the I/O agent circuit is configured to implement coherency mechanisms for transactions associated with the one or more peripheral components; allocating, by the I/O agent circuit, a first transaction, including incrementing one or more of the plurality of counters corresponding to different transaction types than a transaction type of the first transaction; after allocating the first transaction, the I/O agent circuit allocating a second transaction of a different transaction type than the first transaction, including binding the second transaction to a first counter of the one or more counters such that the second transaction is prevented from issuing to the transaction pipeline while the first transaction has not been completed, wherein the second transaction is associated with a particular one of the one or more peripheral components; and completing, by the I/O agent circuit, the first transaction, including decrementing the one or more counters.
9 . The method of claim 8 , further comprising: issuing, by the I/O agent circuit, the second transaction to the transaction pipeline based on the first counter indicating that all transactions that caused the first counter to be incremented have been completed.
10 . The method of claim 9 , further comprising: storing, by the I/O agent circuit for the first transaction, one or more pointers that identify the one or more counters that were incremented based on the first transaction, wherein the decrementing is performed using the one or more pointers.
11 . The method of claim 8 , further comprising: maintaining, by the I/O agent circuit, a linked list of ordered transactions having the same transaction type, wherein the second transaction is included in the linked list and is prevented from issuing to the transaction pipeline while the second transaction is not at a head of the linked list.
12 . The method of claim 11 , wherein at least two transactions in the linked list are bound to different counters of the plurality of counters.
13 . The method of claim 11 , wherein the linked list is associated with a virtual channel included in a plurality of virtual channels that share the plurality of counters.
14 . The method of claim 8 , wherein while the first counter is bound to the second transaction, the first counter is not bound to another transaction.
15 . The method of claim 8 , wherein the first transaction is a posted-based transaction and the second transaction is a non-posted-based transaction.
16 . A non-transitory computer readable medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate an integrated circuit that comprises: a memory controller circuit that is configured to couple to memory and manage access to the memory; an input/output (I/O) agent circuit that includes a transaction pipeline and one or more counters; and a first interconnect that is configured to couple the memory controller circuit and the I/O agent circuit; a second interconnect that is configured to couple the I/O agent circuit and one or more peripheral components; wherein the I/O agent circuit is configured to bridge the one or more peripheral components from the second interconnect to the first interconnect and implement coherency mechanisms for transactions associated with the one or more peripheral components, and wherein the I/O agent circuit is configured to: assign a first counter of the one or more counters to a specific transaction type; increment the first counter assigned to the specific transaction type in response to allocating one or more transactions of a particular, different transaction type than the specific transaction type; based on receiving a request to process a transaction having the specific transaction type, bind the transaction to the first counter such that the transaction is prevented from issuing to the transaction pipeline while the one or more transactions have not been completed, wherein the transaction is associated with a particular one of the one or more peripheral components; and issue the transaction to the transaction pipeline subsequent to detecting, based on the first counter, that the one or more transactions have been completed.
17 . The medium of claim 16 , wherein the input/output (I/O) agent circuit is configured to: perform at least two issuances of a given transaction of the one or more transactions to the transaction pipeline, wherein transaction pipeline is configured to: increment the first counter on an initial pipeline pass of the given transaction; and decrement the first counter on a subsequent pipeline pass of the given transaction.
18 . The medium of claim 16 , wherein the I/O agent circuit is further configured to: based on receiving the request to process the transaction, initialize a second counter and assign the second counter to the specific transaction type; and cease to increment the first counter while the first counter is bound to the transaction.
19 . The medium of claim 16 , wherein the I/O agent circuit is further configured to: based on a retirement of the transaction, release the first counter to the one or more counters such that the first counter is available to bind to another transaction.
20 . The medium of claim 16 , wherein the I/O agent circuit is configured to issue the transaction to the transaction pipeline based further on the transaction being the oldest pending transaction of the specific transaction type.

Description

PRIORITY CLAIM The present application claims priority to U.S. Provisional Appl. No. 63/175,877, filed Apr. 16, 2021, which is incorporated by reference herein in its entirety. BACKGROUND Technical Field This disclosure relates generally to an integrated circuit and, more specifically, to the ordering and processing of transactions at an input/output (I/O) agent. Description of the Related Art Modern computer systems often include a system on a chip (SOC) that integrates many computer components (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) onto an integrated circuit die. These components are normally coupled to memory devices (e.g., random access memory) of the systems via a memory controller. During operation, those components typically perform read and write transactions that involve accessing those memory devices. For read transactions, the components retrieve data from the memory devices without manipulating the data, but for write transactions, the components manipulate the data and then ultimately write it back to one of the memory devices. Also, the components may process the transactions differently based on their transaction type (e.g., non-relaxed ordered transactions versus relaxed ordered transactions). SUMMARY Various embodiments relating to an I/O agent circuit that is configured to implement coherency mechanisms for processing transactions are disclosed. Generally speaking, an SOC is coupled to memory that stores data and is further coupled to and/or includes peripheral components (e.g., a display) that operate on data of that memory. An I/O agent circuit is disclosed that is included in the SOC and is configured to receive requests to perform transactions directed at cache lines of the SOC. The I/O agent circuit may store the transactions in one or more queues of the I/O agent circuit and issue, to a transaction pipeline of the I/O agent circuit from one of those queues, a transaction from a series of transactions enqueued in the queue in a particular order. The I/O agent circuit may further include a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value and assign the first counter to a specific transaction type. Thereafter, the I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a transaction of the specific transaction type, the I/O agent circuit may bind that transaction to the first counter. The I/O agent circuit then may issue the transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value. In some cases, the I/O agent circuit initializes a second counter included in the pool of counters with the initial counter value and assigns the second counter to the specific transaction type. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating example elements of an SOC, according to some embodiments. FIG. 2 is a block diagram illustrating example elements of an I/O agent, according to some embodiments. FIG. 3 is a block diagram illustrating example elements of a transaction pipeline of the I/O agent, according to some embodiments. FIG. 4A is a block diagram illustrating example elements of a table of requests (TOR) of the I/O agent, according to some embodiments. FIG. 4B is a block diagram illustrating example elements of ingress queues of the TOR, according to some embodiments. FIG. 5A is a block diagram illustrating example elements of a process for rejecting one or more transactions, according to some embodiments. FIG. 5B is a block diagram illustrating example elements of a process for rejecting one or more snoop transactions, according to some embodiments. FIG. 6 is a block diagram illustrating example of using counters to track transactions, according to some embodiments. FIG. 7 is a block diagram illustrating example elements of associations between ingress queues and counters, according to some embodiments. FIGS. 8-9 are flow diagrams illustrating example method relating to the rejecting of one or more transactions within the I/O agent, according to some embodiments. FIGS. 10-11 are flow diagrams illustrating example method relating to using counters to track transactions, according to some embodiments. FIG. 12 is a block diagram illustrating example elements of an SOC that includes multiple independent networks as well as local fabrics, according to some embodiments. FIG. 13 is a block diagram illustrating example elements of a network using a ring topology, according to some embodiments. FIG. 14 is a block diagram illustrating example elements of a network using a mesh topology, according to some embodiments. FIG. 15 is a block diagram illustrating example elements of a network using a tree top