US-12625752-B2 - High-speed transmitter circuit system for attenuating inter-channel interference

US12625752B2US 12625752 B2US12625752 B2US 12625752B2US-12625752-B2

Abstract

Disclosed is an inter-channel interference attenuation circuit system, which includes a plurality of channels provided between a memory and a processor and that transmits data received from the memory to the processor, and an interference attenuation circuit module connected one by one to each of the channels, and each of the channels is, a victim channel with respect to the connected interference attenuation circuit module, and an aggressive channel with respect to an adjacent interference attenuation circuit module, which is an interference attenuation circuit module connected to an adjacent channel which is interfered with by its own data transmission, and each of the interference attenuation circuit modules, adjusts an output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels.

Inventors

Young-ha Hwang
Yoochang Kim
Seunghoon Yi
Hee-Cheol Joo
Seung Chae Jung

Assignees

FOUNDATION OF SOONGSIL UNIVERSITY-INDUSTRY COOPERATION

Dates

Publication Date: 20260512
Application Date: 20240612
Priority Date: 20240405

Claims (13)

1 . An inter-channel interference attenuation circuit system comprising: a plurality of channels provided between a memory and a processor and configured to transmit data received from the memory to the processor; and an interference attenuation circuit module connected one by one to each of the channels, and wherein each of the channels is: a victim channel with respect to the connected interference attenuation circuit module; and an aggressive channel with respect to an adjacent interference attenuation circuit module, which is an interference attenuation circuit module connected to an adjacent channel which is interfered with by its own data transmission, and each of the interference attenuation circuit modules is configured to: adjust an output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘0’ to ‘1’; and adjust the output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘1’ to ‘0’, and wherein the each of the interference attenuation circuit modules is configured to: receive an encoder input signal generated by the data transmission of the each aggressive channel from the adjacent interference attenuation circuit module connected to at least one aggressive channel with respect to the connected victim channel; and adjust the output signal of the connected victim channel based on the at least one received encoder input signal.
2 . The inter-channel interference attenuation circuit system of claim 1 , wherein the each of the interference attenuation circuit modules is configured to: when data transmitted by a first aggressive channel with respect to the connected victim channel changes from ‘0’ to ‘1’, receive a first up encoder input signal from a first adjacent interference attenuation circuit module, which is an adjacent interference attenuation circuit module connected to the first aggressive channel; when the data transmitted by the first aggressive channel with respect to the connected victim channel changes from ‘1’ to ‘0’, receive a first down encoder input signal from the first adjacent interference attenuation circuit module; when data transmitted by a second aggressive channel with respect to the connected victim channel changes from ‘0’ to ‘1’, receive a second up encoder input signal from a second adjacent interference attenuation circuit module, which is an adjacent interference attenuation circuit module connected to the second aggressive channel; and when the data transmitted by the second aggressive channel with respect to the connected victim channel changes from ‘1’ to ‘0’, receive a second down encoder input signal from the second adjacent interference attenuation circuit module.
3 . The inter-channel interference attenuation circuit system of claim 2 , wherein the each of the interference attenuation circuit modules further includes: a first switching element provided between an output node connected to the corresponding victim channel and a first voltage source; and a second switching element provided between the output node and a first ground, and wherein the first switching element is configured to: electrically connect the first voltage source to the output node depending on a first control signal generated based on data received by a data input terminal which receives data to be transmitted to the victim channel from the memory, and wherein the second switching element is configured to: electrically connect the output node to the first ground depending on a second control signal generated based on data received by the data input terminal.
4 . The inter-channel interference attenuation circuit system of claim 3 , wherein the each of the interference attenuation circuit modules further includes: a third switching element provided between the output node and a second voltage source; a fourth switching element provided between the output node and the second voltage source; a fifth switching element provided between the output node and a second ground; and a sixth switching element provided between the output node and the second ground, and wherein the third switching element is configured to: electrically connect the second voltage source to the output node depending on a third control signal generated based on the encoder input signals, wherein the fourth switching element is configured to: electrically connect the second voltage source to the output node depending on a fourth control signal generated based on the encoder input signals, wherein the fifth switching element is configured to: electrically connect the second ground to the output node depending on a fifth control signal generated based on the encoder input signals, and wherein the sixth switching element is configured to: electrically connect the second ground to the output node depending on a sixth control signal generated based on the encoder input signals.
5 . The inter-channel interference attenuation circuit system of claim 4 , wherein the each of the interference attenuation circuit modules is configured to: generate the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal, based on whether the first up encoder input signal is received, whether the first down encoder input signal is received, whether the second up encoder input signal is received, and whether the second down encoder input signal is received, respectively.
6 . The inter-channel interference attenuation circuit system of claim 5 , wherein the each of the interference attenuation circuit modules is configured to: generate the third control signal when the first down encoder input signal from the first adjacent interference attenuation circuit module is received and the second up encoder input signal from the second adjacent interference attenuation circuit module is not received; generate the fourth control signal when the second down encoder input signal from the second adjacent interference attenuation circuit module is received and the first up encoder input signal from the first adjacent interference attenuation circuit module is not received; generate the fifth control signal when the first up encoder input signal from the first adjacent interference attenuation circuit module is received and the second down encoder input signal from the second adjacent interference attenuation circuit module is not received; and generate the sixth control signal when the second up encoder input signal is received from the second adjacent interference attenuation circuit module and the first down encoder input signal is not received from the first adjacent interference attenuation circuit module.
7 . The inter-channel interference attenuation circuit system of claim 6 , wherein the each of the interference attenuation circuit modules further includes: an up signal generating driver provided between a gate terminal of the first switching element and the data input terminal and configured to generate an up encoder input signal based on a change in data received through the data input terminal; and a down signal generating driver provided between a gate terminal of the second switching element and the data input terminal and configured to generate a down encoder input signal based on the change in the data received through the data input terminal.
8 . The inter-channel interference attenuation circuit system of claim 7 , wherein the each of the interference attenuation circuit modules is configured to: receive the first up encoder input signal from the up signal generating driver of the first adjacent interference attenuation circuit module; receive the first down encoder input signal from the down signal generating driver of the first adjacent interference attenuation circuit module; receive the second up encoder input signal from the up signal generating driver of the second adjacent interference attenuation circuit module; and receive the second down encoder input signal from the down signal generating driver of the second adjacent interference attenuation circuit module.
9 . The inter-channel interference attenuation circuit system of claim 8 , wherein the each of the interference attenuation circuit modules further includes: a pulse encoder configured to generate a driver input signal and a switch input signal based on the encoder input signal; at least one pre-driver electrically connected to the pulse encoder and configured to generate a strength control signal with a magnitude corresponding to a fine-tuning digital code when the fine-tuning digital code and the driver input signal are received; and at least one switch module electrically connected to the pulse encoder and the pre-driver, and configured to generate a control signal with a magnitude corresponding to the strength control signal and a range adjustment digital code when the strength control signal, the range adjustment digital code, and the switch input signal are received.
10 . The inter-channel interference attenuation circuit system of claim 9 , wherein the pre-driver includes: an up pre-driver and a down pre-driver, and wherein the pulse encoder is configured to: when the interference attenuation circuit module receives at least one of the first up encoder input signal and the second up encoder input signal, transmit the driver input signal to the up pre-driver; and when the interference attenuation circuit module receives at least one of the first down encoder input signal and the second down encoder input signal, transmit the driver input signal to the down pre-driver.
11 . The inter-channel interference attenuation circuit system of claim 10 , wherein the pulse encoder is configured to: when the first down encoder input signal is received and the second up encoder input signal is not received, generate a first up switch input signal; when the second down encoder input signal is received and the first up encoder input signal is not received, generate a second up switch input signal; when the first up encoder input signal is received and the second down encoder input signal is not received, generate a first down switch input signal; and when the second up encoder input signal is received and the first down encoder input signal is not received, generate a second down switch input signal.
12 . The inter-channel interference attenuation circuit system of claim 11 , wherein the switch module includes: a first up switch module and a second up switch module, and wherein the first up switch module is configured to: when the strength control signal from the up pre-driver is received and the first up switch input signal from the pulse encoder is received, generate the third control signal with a magnitude corresponding to the strength control signal and the range adjustment digital code so as to be transmitted to a gate terminal of the third switching element, and wherein the second up switch module is configured to: when the strength control signal from the up pre-driver is received and the second up switch input signal from the pulse encoder is received, generate the fourth control signal with a magnitude corresponding to the strength control signal and the range adjustment digital code so as to be transmitted to a gate terminal of the fourth switching element.
13 . The inter-channel interference attenuation circuit system of claim 11 , wherein the switch module includes: a first down switch module and a second down switch module, and wherein the first down switch module is configured to: when the strength control signal from the down pre-driver is received and the first down switch input signal from the pulse encoder is received, generate the fifth control signal with a magnitude corresponding to the strength control signal and the range adjustment digital code so as to be transmitted to a gate terminal of the fifth switching element, and wherein the second down switch module is configured to: when the strength control signal from the down pre-driver is received and the second down switch input signal from the pulse encoder is received, generate the sixth control signal with a magnitude corresponding to the strength control signal and the range adjustment digital code so as to be transmitted to a gate terminal of the sixth switching element.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0046445 filed on Apr. 5, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND Embodiments of the present disclosure described herein relate to a high-speed transmitter circuit and a system that may cancel or attenuate inter-channel interference phenomena. This present disclosure is carried out from research conducted as part of the PIM artificial intelligence semiconductor core technology development (R&D) (manufacturing) (Project identification number: 1415184150, Project number: 00155730, Research project name: Development of low-noise circuit technology for module interface for high-speed SCM memory, Project management agency: Korea Institute of Industrial Technology Planning and Evaluation, research period: 2023 Jan. 1 to 2023 Dec. 31) of the Ministry of Trade, Industry and Energy. Meanwhile, there is no property interest of the Korean government in any aspect of the present disclosure. Depending on how Processing-in-Memory (PIM) is implemented, it may be divided into a Processing-in-chip, which adds logic that performs calculations in the same process as a memory cell, and a Processing-near-memory, which produces a separate package and modularizes it with the memory, or uses a stacked method using Through Silicon Via (TSV). PIM semiconductors based on high-bandwidth stacked memory are known as a semiconductor chip technology that is implemented with an NPU and a GPU to maximize memory data access and data processing performance to enable real-time artificial intelligence calculation of large-scale data. Low-noise memory interface technology for the PIM is a core circuit technology that overcomes memory barriers in high-performance computing systems implemented by high-bandwidth channels and low-noise interface circuits connecting the PIM semiconductors and the high-performance GPU/NPU. SUMMARY Embodiments of the present disclosure provide an inter-channel interference attenuation circuit and a system that may improve signal quality by removing or attenuating inter-channel interference phenomena. In addition, embodiments of the present disclosure provide an inter-channel interference attenuation circuit and a system that may be implemented with low power and a small area compared to the conventional art, by implementing a circuit at the transmitting end that may cancel or attenuate inter-channel interference at the receiving end. In addition, embodiments of the present disclosure provide an inter-channel interference attenuation circuit and a system that may control the attenuation of inter-channel interference compared to the conventional art. According to an embodiment of the present disclosure, an inter-channel interference attenuation circuit system includes a plurality of channels provided between a memory and a processor and that transmits data received from the memory to the processor, and an interference attenuation circuit module connected one by one to each of the channels, and each of the channels is, a victim channel with respect to the connected interference attenuation circuit module, and an aggressive channel with respect to an adjacent interference attenuation circuit module, which is an interference attenuation circuit module connected to an adjacent channel which is interfered with by its own data transmission, and each of the interference attenuation circuit modules, adjusts an output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘0’ to ‘1’, and adjusts the output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘1’ to ‘0’. According to an embodiment, the each of the interference attenuation circuit modules, may receive an encoder input signal generated by the data transmission of the each aggressive channel from the adjacent interference attenuation circuit module connected to at least one aggressive channel with respect to the connected victim channel, and may adjust the output signal of the connected victim channel based on the at least one received encoder input signal. According to an embodiment, the each of the interference attenuation circuit modules, when data transmitted by a first aggressive channel with respect to the connected victim channel changes from ‘0’ to ‘1’, may receive a first up encoder input signal from a first adjacent interference attenuation circuit module, which is an adjacent interference attenuation circuit module connected to the first aggressive channel, when the data