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US-12625756-B2 - Processor crash analysis using register sampling

US12625756B2US 12625756 B2US12625756 B2US 12625756B2US-12625756-B2

Abstract

Systems and methods are disclosed for processor crash analysis using register sampling. For example, an integrated circuit may include a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register (e.g., a machine exception program counter register) that is configured to store a program counter value that was current when an exception occurred; a data store connected to the exception program counter register via an ingress port that is configured to store a copy of an exception program counter value responsive to retirement of an instruction; and an exception program counter capture register, configured to store an exception program counter value from the second data store responsive to a reset signal for the processor core.

Inventors

  • Ernest L. Edgar
  • Bruce Ableidinger

Assignees

  • SiFive, Inc.

Dates

Publication Date
20260512
Application Date
20220711

Claims (18)

  1. 1 . An integrated circuit for executing instructions comprising: a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register that is configured to store a program counter value that was current when an exception occurred; a trace encoder circuitry outside the processor core and connected to the processor core via an ingress port, the trace encoder circuitry comprising: a first sampling data store connected to the program counter register via the ingress port that is configured to store a copy of a program counter value for an instruction responsive to retirement of the instruction, wherein the first data store is outside the processor core and is connected to the processor core via the ingress port; a second sampling data store connected to the exception program counter register via the ingress port that is configured to store a copy of an exception program counter value responsive to retirement of the instruction; a program counter capture register, configured to store a program counter value from the first sampling data store responsive to a reset signal for the processor core; and an exception program counter capture register, configured to store an exception program counter value from the second sampling data store responsive to the reset signal for the processor core.
  2. 2 . The integrated circuit of claim 1 , in which values stored in the program counter capture register and the exception program counter capture register are retained through a reset of the processor core caused by the reset signal.
  3. 3 . The integrated circuit of claim 1 , in which the exception program counter register is a machine exception program counter register.
  4. 4 . The integrated circuit of claim 1 , in which the exception program counter register is a supervisor exception program counter register.
  5. 5 . The integrated circuit of claim 1 , in which the exception program counter register is a user exception program counter register.
  6. 6 . The integrated circuit of claim 1 , in which the exception program counter register is a virtual supervisor exception program counter register.
  7. 7 . A method comprising: sampling a program counter register responsive to retirement of instructions by a processor core, wherein a sampled value of the program counter register is stored in a first sampling data store outside the processor core, and wherein the first sampling data store is connected to the processor core via an ingress port; sampling an exception program counter register responsive to retirement of instructions by the processor core, wherein a sampled value of the exception program counter register is stored in a second sampling data store outside the processor core, wherein the exception program counter register is configured to store a program counter value that was current when an exception occurred; storing the sampled value of the program counter register from the first sampling data store in a program counter capture register responsive to a reset signal for the processor core; storing the sampled value of the exception program counter register from the second sampling data store in an exception program counter capture register responsive to the reset signal for the processor core; and after a reset of the processor core caused by the reset signal, reading the program counter capture register and the exception program counter capture register.
  8. 8 . The method of claim 7 , wherein the program counter register and the exception program counter register are sampled via the ingress port.
  9. 9 . The method of claim 7 , in which the exception program counter register is a machine exception program counter register.
  10. 10 . The method of claim 7 , in which the exception program counter register is a supervisor exception program counter register.
  11. 11 . The method of claim 7 , in which the exception program counter register is a user exception program counter register.
  12. 12 . The method of claim 7 , in which the exception program counter register is a virtual supervisor exception program counter register.
  13. 13 . A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising: a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register that is configured to store a program counter value that was current when an exception occurred; a trace encoder circuitry outside the processor core and connected to the processor core via an ingress port, the trace encoder circuitry comprising: a first sampling data store connected to the program counter register via the ingress port that is configured to store a copy of a program counter value for an instruction responsive to retirement of the instruction, wherein the first data store is outside the processor core and is connected to the processor core via the ingress port; a second sampling data store connected to the exception program counter register via the ingress port that is configured to store a copy of an exception program counter value responsive to retirement of the instruction; a program counter capture register, configured to store a program counter value from the first sampling data store responsive to a reset signal for the processor core; and an exception program counter capture register, configured to store an exception program counter value from the second sampling data store responsive to the reset signal for the processor core.
  14. 14 . The non-transitory computer readable medium of claim 13 , in which values stored in the program counter capture register and the exception program counter capture register are retained through a reset of the processor core caused by the reset signal.
  15. 15 . The non-transitory computer readable medium of claim 13 , in which the exception program counter register is a machine exception program counter register.
  16. 16 . The non-transitory computer readable medium of claim 13 , in which the exception program counter register is a supervisor exception program counter register.
  17. 17 . The non-transitory computer readable medium of claim 13 , in which the exception program counter register is a user exception program counter register.
  18. 18 . The non-transitory computer readable medium of claim 13 , in which the exception program counter register is a virtual supervisor exception program counter register.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a 371 of International Application No. PCT/US2022/036694, filed on Jul. 11, 2022, which claims the benefit of U.S. Provisional Application 63/221,262 filed on Jul. 13, 2021. The entire contents of these applications are incorporated herein by reference in their entirety. TECHNICAL FIELD This disclosure relates to processor crash analysis using register sampling. BACKGROUND Instruction tracing is a technique used to analyze the history of instructions executed by a processor. Information associated with one or more instructions may be collected from a processor executing the instructions. The information collected may be analyzed to determine system performance and to help identify possible optimizations for improving the system. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. FIG. 1 is block diagram of an example of a system for executing instructions with processor crash analysis using register capture. FIG. 2 is flow chart of an example of a technique for processor crash analysis using register capture. FIG. 3 is a block diagram of an example of a system for facilitating generation of a circuit representation. DETAILED DESCRIPTION Overview Disclosed herein are implementations of processor crash analysis using register capture. An integrated circuit (e.g., a processor or microcontroller) may be configured to sample a program counter and an exception program counter (e.g., a machine exception program counter) of a processor core of the integrated circuit responsive to instruction retirement. The sampled register values may be stored in capture registers responsive to a reset signal for the processor core to preserve these register values through a reset that results from the reset signal. For example, the program counter and a machine exception program counter register values may be sampled using signals in an ingress port of the processor core. The ingress port may include signals, such as, a “reset” signal indicating that core is being reset, a “iretire” signal indicating that an instruction has been executed and an “iaddr” which indicates an address (the PC) of the instruction being retired. When an MEPC capture option is activated, the MEPC register is also connected from the core to sampling circuitry outside of the processor core (e.g., in a trace encoder circuitry). This information may be used in capture hardware to preserve parts of the processor core state through a reset. The Capture hardware may be configured such that, when iretire occurs, iaddr and mepc are stored into sampling registers. When a reset occurs due to a crash, the latest values in the sampling registers may be copied to the capture registers. Boot code following the reset can read out the capture registers to get the values of PC and MEPC at the time of the crash. PC Sampling Unit Since the Trace Encoder directly connects to the core's TracedInstruction output bundle, it is relatively easy to add a PC Sampling Unit that provides a read-only interface to the current execution address. In some hang scenarios, this information is useful to be able to pinpoint what the core was doing just prior to the hang. This interface can also be used for non-intrusive statistical profiling. In systems with a watchdog timer that resets the core upon timeout, it is also useful to capture the address of the last retired instruction so that it can be read out as part of a crash analysis. The pcCapture registers capture a new sample on each occurrence of the core reset. Register Descriptions This section describes the functionality of the PC Sampling Unit registers for an example implementation of a system for processor crash analysis using register capture. TABLE 1PC Sample Control Register PC Sample Control Register (pcControl)Address Offset 0 × 0100BitsField NameAttr.Rst.Description0pcActiveRW0 × 0Master enable/reset for PC SamplingUnit. pcActive must be set to 1 beforeany other fields in pcControl areprogrammed. This bit is reset to 0 bythe trace reset input and must be set to0 × 1 in order to perform sampling. Theclock to the PC Sampling Unit may begated off when pcActive = 0. Note thatpcActive is not dependent onteActive, so the PC Sampling Unit canbe enabled while the rest of the traceencoder is disabled.[31:1]ReservedRO0 × 0 TABLE 2PC Capture and Sample Implementation RegisterPC Capture/Sample Implementation Register (pcImp))Address Offset 0 × 0104BitsField NameAttr.Rst.Description[15:0]pcCaptureFieldsROpresetBitmap indicating which core registersother than PC are present in the PCCapture register range. RC is alwayspresent. Capture registers arepopulated down