US-12625763-B2 - Data error correction method and apparatus, memory controller, and system

Abstract

When a memory controller reads target data in a memory, the memory controller reads the target data and first check code of the target data from the memory. The memory controller checks the target data using the first check code. If the check fails, it indicates that error data exists in the target data. The memory controller then performs error correction on the target data using the first check code. After failing to perform error correction on the target data using the first check code in the memory, the memory controller performs error correction on the target data using the second check code in the secondary storage.

Inventors

• Wei Pan
• JUNPING LUO

Assignees

• HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260512

Application Date

20240606

Priority Date

20211209

Claims (20)

1. 1 . A method applied to a memory controller, wherein the method comprises: obtaining target data; generating a first check code based on the target data and a second check code based on the target data; storing the target data and the first check code in a memory; storing the second check code in a secondary storage; reading, from the memory, the target data and the first check code; performing error correction on the target data using the first check code; reading, after error correction performed on the target data using the first check code fails, the second check code from the secondary storage; and performing, using the second check code, error correction on the target data.
2. 2 . The method of claim 1 , wherein performing, using the second check code, the error correction on the target data comprises performing error correction on the target data using the second check code and the first check code.
3. 3 . The method of claim 2 , wherein the first check code and the second check code are different.
4. 4 . The method of claim 1 , wherein the secondary storage comprises a part or all of a storage class memory (SCM), a solid-state drive (SSD), a hard disk drive (HDD), or a random-access memory.
5. 5 . The method of claim 1 , wherein the first check code comprises first data and the second check code comprises the first data.
6. 6 . The method of claim 1 , further comprising reporting, to a processor after error correction performed on the target data using the second check code fails, an error message indicating at least one of error data in the target data or a storage position of the error data.
7. 7 . A computer program product comprising instructions that are stored on a computer-readable medium and that, when executed by a processor, cause an apparatus to: obtain target data; generate a first check code based on the target data and a second check code based on the target data; store the target data and the first check code in a memory; store the second check code in a secondary storage; read, from the memory, the target data and the first check code; perform error correction on the target data using the first check code; read, after error correction performed on the target data using the first check code fails, the second check code from the secondary storage; and perform, using the second check code, error correction on the target data.
8. 8 . The computer program product of claim 7 , wherein the instructions, when executed by the processor, further cause the apparatus to perform error correction on the target data using the second check code and the first check code.
9. 9 . The computer program product of claim 8 , wherein the first check code and the second check code are different.
10. 10 . The computer program product of claim 7 , wherein the secondary storage comprises a part or all of a storage class memory (SCM), a solid-state drive (SSD), a hard disk drive (HDD), or a random-access memory.
11. 11 . The computer program product of claim 7 , wherein the first check code comprises first data and the second check code comprises the first data.
12. 12 . A system comprising: a memory configured to store target data and first check code of the target data; a secondary storage configured to store second check code of the target data; a secondary controller; and a memory controller coupled to the memory, the secondary controller, and the secondary storage, wherein the memory controller is configured to: obtain the target data; generate the first check code based on the target data and the second check code based on the target data; store the target data and the first check code in the memory; provide an instruction to the secondary controller to store the second check code in the secondary storage; read, from the memory, the target data and the first check code of the target data; perform error correction on the target data using the first check code; read, after error correction performed on the target data using the first check code fails, the second check code of the target data from the secondary storage; and perform, using the second check code, error correction on the target data, and wherein the secondary controller configured to store, based on the instruction of the memory controller, the second check code in the secondary storage.
13. 13 . The system of claim 12 , wherein when performing error correction on the target data using the second check code, the memory controller is further configured to perform error correction on the target data using the second check code and the first check code.
14. 14 . The system of claim 13 , wherein the first check code and the second check code are different.
15. 15 . The system of claim 12 , wherein the secondary storage comprises a part or all of a storage class memory (SCM), a solid-state drive (SSD), a hard disk drive (HDD), or a random-access memory.
16. 16 . The system of claim 12 , wherein the first check code comprises first data and the second check code comprises the first data.
17. 17 . The system of claim 12 , wherein the memory controller is further configured to report, to a processor after error correction performed on the target data using the second check code fails, an error message indicating at least one of error data in the target data or a storage position of the error data.
18. 18 . The system of claim 12 , wherein the memory controller is further configured to feed back, to a processor after error correction performed on the target data using the second check code succeeds, corrected target data.
19. 19 . The method of claim 1 , further comprising feeding back, to a processor after error correction performed on the target data using the second check code succeeds, corrected target data.
20. 20 . The computer program product of claim 7 , wherein the instructions, when executed by the processor, further cause the apparatus to: report, after error correction performed on the target data using the second check code fails, an error message indicating at least one of error data in the target data or a storage position of the error data; and feed back, after error correction performed on the target data using the second check code succeeds, corrected target data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2022/136779 filed on Dec. 6, 2022, which claims priority to Chinese Patent Application No. 202111498708.0 filed on Dec. 9, 2021. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD This application relates to the field of storage technologies, and in particular, to a data error correction method and apparatus, a memory controller, and a system. BACKGROUND A memory is configured to: temporarily store computing data of a processor in a computer, and data exchanged with an external storage such as a hard disk. A memory controller is located inside the computer, is connected to the processor and the memory in the computer, and is configured to manage the memory and be responsible for data exchange between the memory and the processor. When the memory controller reads data under indication of the processor, in addition to reading the data from the memory, the memory controller further reads check code of the data from the memory, and checks the read data by using the check code to determine whether an error exists in the data. If an error exists in the read data, the memory controller may perform error correction on the read data by using the check code, and feeds back corrected data to the processor if the error correction succeeds. From a perspective of data error correction, a larger amount of data of the check code indicates a stronger error correction capability of the check code, and error correction can be performed on a large amount of error data in the data. However, considering limited storage space of the memory, in actual application, the check code is not allowed to occupy much storage space. Currently, the check code stored in the memory can usually be used to perform error correction on only single-bit error data existing in the data. When multi-bit error data exists in the data, an error correction effect cannot be achieved. SUMMARY This application provides a data error correction method and apparatus, a memory controller, and a system, to improve a data error correction capability in a memory. According to a first aspect, an embodiment of this application provides a data error correction method, and the method may be performed by a memory controller. When the memory controller may need to read target data in the memory, the memory controller may read the target data and first check code of the target data from the memory. The memory controller may check the target data by using the first check code. If the check fails, it indicates that error data exists in the target data. The memory controller may perform error correction on the target data by using the first check code. After the memory controller fails to perform error correction on the target data by using the first check code, the memory controller may obtain second check code of the target data in a secondary storage. After the memory controller obtains the second check code, the memory controller performs error correction on the target data by using the second check code. According to the foregoing method, after failing to perform error correction on the target data by using the first check code in the memory, the memory controller can further perform error correction on the target data by using the second check code in the secondary storage, to ensure that the error correction can be implemented on the target data, and improve a data error correction capability. In a possible implementation, when performing error correction on the target data by using the second check code, the memory controller may perform error correction on the target data by using only the second check code, or may perform error correction on the target data by using the second check code and the first check code. According to the foregoing method, after the error correction performed on the target data by using the first check code fails, the memory controller may flexibly perform error correction on the target data by using the second check code in different manners. This method is applicable to different scenarios. In a possible implementation, after the memory controller may need to write the target data into the memory, and after obtaining the target data, the memory controller may generate the first check code and the second check code of the target data based on the target data. The memory controller may store the target data and the first check code in the memory, and the memory controller may store the second check code in the secondary storage. According to the foregoing method, the first check code and the second check code that are generated based on the target data may be separately stored in different storages, to ensure that the check code does not occupy large memory space, and ensure the data error correction capability in the memory. In a possible implementation, the s