US-12625766-B2 - Semiconductor memory device-directed error check and scrub

Abstract

Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.

Inventors

• Sujeet Ayyapureddi

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240730

Claims (18)

1. 1 . A memory device comprising: a memory array comprising a plurality of code words; an error-correction code (ECC) circuit coupled with the memory array; a mode register configured to store a code word address and a valid indicator; and circuitry coupled with the memory array, the mode register, and the ECC circuit, the circuitry configured to: receive, from a host device, an error check and scrub (ECS) command; determine, in response to receiving the ECS command and based on the valid indicator of the mode register, that an error was detected in the memory array prior to receiving the ECS command; and perform, in response to determining that an error was detected in the memory array prior to receiving the ECS command, an ECS procedure on a code word associated with the error using the ECC circuit, wherein the code word on which the ECS procedure is performed corresponds to the code word address stored in the mode register; and a Data Mask (DM) pin configured to transmit an indication to the host device that the error was detected.
2. 2 . The memory device of claim 1 , wherein the code word address comprises a column address, a row address, a bank address, and a bank group address.
3. 3 . The memory device of claim 1 , wherein performing the ECS procedure on the code word comprises: retrieving the code word from the memory array; updating, using the ECC circuit, the retrieved code word based on an ECC function; and storing the updated code word to the memory array.
4. 4 . The memory device of claim 1 , wherein the circuitry is further configured to: receive, from the host device, a read command directed to the memory array; retrieve, in response to the received read command, data from the memory array, the data comprising a second code word; detect at least one error in the second code word using the ECC circuit, wherein the second code word is associated with an address; and store the address in a mode register.
5. 5 . The memory device of claim 4 , wherein determining that an error was detected in the memory array prior to receiving the ECS command is based on the address stored in the mode register, and wherein the code word on which the ECS procedure is performed corresponds to the address stored in the mode register.
6. 6 . The memory device of claim 4 , wherein the memory device is configured, in response to detecting the at least one error in the second code word, to transmit the indication to the host device.
7. 7 . The memory device of claim 6 , wherein the memory device further comprises a Compute Express Link (CXL) interface.
8. 8 . The memory device of claim 6 , wherein the memory device further comprises a DDR6 interface, wherein the DDR6 interface comprises a sideband bus, and wherein the memory device transmits the indication to the host device that an error was detected using the sideband bus.
9. 9 . The memory device of claim 1 , wherein the circuitry is further configured to clear, after performing the ECS procedure on a code word associated with the error, a valid bit associated with the error.
10. 10 . The memory device of claim 1 , the memory device further comprising a plurality of mode registers, wherein each mode register is configured to store a code word address and a valid bit, and wherein: determining that an error was detected in the memory array prior to receiving the ECS command comprises identifying at least one mode register with an asserted valid bit; and performing the ECS procedure comprises selecting one of the identified mode registers, wherein the code word on which the ECS procedure is performed is associated with the code word address stored in the selected mode register.
11. 11 . The memory device of claim 10 , wherein selecting one of the identified mode registers comprises: determining, from the identified mode registers, which mode register's valid bit has been asserted the longest; and selecting the mode register with the longest-asserted valid bit.
12. 12 . The memory device of claim 10 , wherein the circuitry is further configured to perform a plurality of ECS procedures without receiving an ECS command from the host device.
13. 13 . The memory device of claim 12 , wherein each of the plurality of ECS procedures operates on a different code word than the previous ECS procedure of the plurality of ECS procedures, and wherein the circuitry is further configured to perform the plurality of ECS procedures so that all code words in the memory array are operated on during a 24-hour period.
14. 14 . The memory device of claim 1 , wherein the circuitry is further configured to: perform, in response to determining that no error was detected in the memory array prior to receiving the ECS command, an ECS procedure on a second code word, wherein the second code word is associated with an address stored in an address counter.
15. 15 . A method comprising: receiving, at a memory device, a read command from a host device coupled to the memory device; retrieving, in response to the received read command, data from a memory array of the memory device, wherein the data comprises a code word; detecting at least one error in the code word of the retrieved data; storing, in response to detecting the at least one error in the code word, a memory array address associated with the code word to a mode register; sending, in response to detecting the at least one error in the code word, an indication to the host device that an error was detected in response to the read command, wherein the indication is sent using a Data Mask (DM) pin of the memory device; and performing an internal read-modify-write cycle on the code word associated with the memory array address in the mode register, wherein the internal read-modify-write cycle comprises correcting the at least one error in the code word.
16. 16 . The method of claim 15 , wherein correcting the at least one error in the code word comprises using an ECC circuit of the memory device.
17. 17 . The method of claim 15 , the method further comprising: clearing, after performing the internal read-modify-write cycle on the code word, the memory array address from the mode register.
18. 18 . The method of claim 15 , wherein the memory device is coupled to the host device via a sideband bus to which at least one other memory device is coupled, and wherein the memory device sends the indication that an error was detected using the sideband bus.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) The present application claims priority to U.S. Provisional Patent Application No. 63/545,021, filed Oct. 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to a memory device, and more specifically, relates to error check and scrub directed by a semiconductor memory device. BACKGROUND Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices may be volatile or non-volatile and can be of various types, such as magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and others. Information is stored in various types of RAM by charging a memory cell to have different states. Improving RAM memory devices, generally, can include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates a simplified block diagram schematically illustrating a memory device in accordance with an embodiment of the present technology. FIG. 2 is a simplified block diagram of an example memory device illustrating various components for performing an error check and scrub (ECS) procedure in accordance with an embodiment of the present disclosure. FIG. 3 is an example flow diagram for directing an ECS procedure in accordance with embodiments of the present disclosure. FIG. 4 is an example flow diagram for performing an ECS procedure in accordance with embodiments of the present disclosure. FIG. 5 is a simplified block diagram schematically illustrating an example memory system in accordance with an embodiment of the present disclosure. FIG. 6 is a block diagram of an example computer system in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION Methods, systems, and apparatuses for semiconductor memory devices (e.g., DRAM) are disclosed, which include an error check and scrub (ECS) procedure that may be directed by the memory devices (i.e., memory devices with directed ECS). The described ECS procedure may be regarded as “directed” by the memory devices in that the ECS procedure may be performed in response to information from the memory devices (e.g., indicating the detection of an error in the memory device). The described ECS procedure may be further regarded as “directed” by the memory devices in that the ECS procedure may prioritize operating on memory device addresses identified by the memory devices (e.g., memory device addresses where errors have been detected). Some semiconductor memory devices, such as DRAM, store information as a charge accumulated in cell capacitors (“cells”), with the cells organized into rows. The charge accumulated in the cell capacitors may escape from the cell capacitor (which may be referred to as “leakage”) to surrounding components connected to the cell capacitor (e.g., metal lines, semiconductor junctions of switching transistors) due to a voltage difference between the capacitor and the surrounding components, in some cases. As a result, a cell's charge may change. A cell's charge may also change in response to a particle strike. Errors may occur if a cell's charge has changed enough that the charge is interpreted as a wrong logic value (i.e., the bit has “flipped” from a correct logic value, resulting in a bit “flip” error or bit error). In some cases, memory devices may be configured to perform an error-correction code (ECC) function (e.g., using an on-die ECC engine or ECC circuit) that can detect and correct one or more errors in data stored in the memory array (e.g., a code word). In some cases, the ECC function is performed as part of a read operation of the memory device (e.g., in response to a read command issued from a host coupled to the memory device), such that corrected read data is provided to the host. However, in conventional memory devices, corrected read data generated by the ECC function during a read operation is not written back to the memory device (i.e., the corrected data is sent to the host, but errors will remain in the data resident in the memory device itself). In some cases, the ECC function is performed as part of an ECS operation, in which the memory device reads data bits, corrects errors that are detected (e.g., using the ECC function), and writes back the corrected data bits to the memory device. That is, the ECS operation scrubs the memory device for errors. The ECS operation may involve performing an ECS