US-12625769-B2 - Error handling method based on redundant array of independent disks type check and related memory controller and data storage device

US12625769B2US 12625769 B2US12625769 B2US 12625769B2US-12625769-B2

Abstract

An error handling method for use in a flash memory includes: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory.

Inventors

Hsiao-Chang YEN
Tsu-Han Lu

Assignees

SILICON MOTION, INC.

Dates

Publication Date: 20260512
Application Date: 20240429
Priority Date: 20240229

Claims (20)

1 . An error handling method for use in a flash memory, comprising: performing an error correction code (ECC) verification operation on a page of data read from the flash memory, wherein the page of data corresponds to one or more ECC codewords; in response to a decoding failure of the ECC verification operation on the page of data occurs or written data on which a programming failure occurs, determining verification data corresponding to the page of data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory.
2 . The error handling method of claim 1 , wherein the verification data is redundant array of independent disks (RAID) verification data; and the RAID verification data is generated by performing an exclusive-OR operation on the page of data and one or more stored data in the flash memory, or the RAID verification data is generated by performing an exclusive-OR operation on the written data and one or more stored data in the flash memory.
3 . The error handling method of claim 1 , wherein the step of selecting the data to be moved comprises: determining the data to be moved according to one or more stored data in the flash memory that are associated with the verification data.
4 . The error handling method of claim 3 , wherein the step of selecting the data to be moved comprises: for each of the one or more stored data associated with the verification data: determining whether the stored data is valid data based on a logical address of the stored data; and setting the stored data as the data to be moved if the stored data is valid data.
5 . The error handling method of claim 4 , wherein the step of determining whether the stored data is valid data comprises: querying a flash-to-host (F2H) address mapping table to determine whether the stored data has a corresponding entry in the F2H address mapping table; determining whether the stored data is valid data based on the F2H address mapping table if the stored data has a corresponding entry in F2H address mapping table; and determining whether the stored data is valid data based on a host-to-flash (H2F) address mapping table if the stored data does not have a corresponding entry in the flash memory.
6 . The error handling method of claim 1 , further comprising: determining whether the page of data with the decoding failure or the written data with the programming failure is read from or programmed to in an active storage space of the flash memory; not performing the data movement operation if page of data with the decoding failure or the written data with the programming failure is read from or programmed to the active storage space; and performing the data movement operation if page of data with the decoding failure or the written data with the programming failure is not read from or not programmed to the active storage space.
7 . The error handling method of claim 6 , further comprising: writing dummy data into a remaining available space of the active storage space if the page of data with the decoding failure or the written data with the programming failure is read from or programmed to the active storage space and the flash memory is about to enter an idle state; and performing the data movement operation after writing the dummy data.
8 . The error handling method of claim 6 , wherein the active storage space is an active bank of multiple banks of a super block of the flash memory and the target storage space is a different one of the multiple banks of the super block than the active bank.
9 . The error handling method of claim 8 , wherein each of the multiple banks is utilized to store the verification data and one or more stored data associated with and protected by the verification data.
10 . The error handling method of claim 1 , wherein the decoding failure is one of a hard decoding failure of an error correction code verification operation and a soft decoding failure of an error correction code verification operation and a decoding failure of RAID verification operation.
11 . A memory controller for use in a flash memory, comprising: a storage unit configured to store program code; a processing unit configured to execute the program code to perform error handling procedure on the flash memory, comprising: performing an error correction code (ECC) verification operation on a page of data read from the flash memory, wherein the page of data corresponds to one or more ECC codewords; in response to a decoding failure of the ECC verification operation on the page of data occurs or written data on which a programming failure occurs, determining verification data corresponding to the page of data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory.
12 . The memory controller of claim 11 , wherein the verification data is redundant array of independent disks (RAID) verification data; and the RAID verification data is generated by performing an exclusive-OR operation on the page of data and one or more stored data in the flash memory, or the RAID verification data is generated by performing an exclusive-OR operation on the written data and one or more stored data in the flash memory.
13 . The memory controller of claim 11 , wherein the processing unit is configured to perform operations of: determining the data to be moved according to one or more stored data in the flash memory that are associated with the verification data.
14 . The memory controller of claim 13 , wherein the processing unit is configured to perform operations of: for each of the one or more stored data associated with the verification data: determining whether the stored data is valid data based on a logical address of the stored data; and setting the stored data as the data to be moved if the stored data is valid data.
15 . The memory controller of claim 14 , wherein the processing unit is configured to perform operations of: querying a flash-to-host (F2H) address mapping table to determine whether the stored data has a corresponding entry in the F2H address mapping table; determining whether the stored data is valid data based on the F2H address mapping table if the stored data has a corresponding entry in F2H address mapping table; and determining whether the stored data is valid data based on a host-to-flash (H2F) address mapping table if the stored data does not have a corresponding entry in the flash memory.
16 . The memory controller of claim 11 , wherein the processing unit is configured to perform operations of: determining whether the page of data with the decoding failure or the written data with the programming failure is read from or programmed to in an active storage space of the flash memory; not performing the data movement operation if the page of data with the decoding failure or the written data with the programming failure is read from or programmed to the active storage space; and performing the data movement operation if the page of data with the decoding failure or the written data with the programming failure is not read from or not programmed to the active storage space.
17 . The memory controller of claim 16 , further comprising: writing dummy data into a remaining available space of the active storage space if the page of data with the decoding failure or the written data with the programming failure is read from or programmed to the active storage space and the flash memory is about to enter an idle state; and performing the data movement operation after writing the dummy data.
18 . The memory controller of claim 16 , wherein the active storage space is an active bank of multiple banks of a super block of the flash memory and the target storage space is a different one of the multiple banks of the super block than the active bank.
19 . The memory controller of claim 18 , wherein each of the multiple banks is utilized to store the verification data and one or more stored data associated with and protected by the verification data.
20 . The memory controller of claim 11 , wherein the decoding failure is one of a hard decoding failure of an error correction code verification operation and a soft decoding failure of an error correction code verification operation and a decoding failure of RAID verification operation.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory, and in particular, refers to an error handling method based on redundant array of independent Disks verification, as well as related memory controllers and data storage devices. 2. Description of the Prior Art Error correction coding (ECC) is relied upon to correct reading errors in the flash memory storage devices. Before data is stored into the flash memory storage devices, it can be encoded by an ECC encoder to generate protection information. Such information can be stored as ECC codewords together with original data. In addition, the flash memory storage devices also rely upon a redundant array of independent Disks (RAID)-type data protection mechanism, which utilizes RAID parity to implement data verification and error correction. The RAID-type verification and correction can be used to handle errors that exceed the correction capabilities of ECC. Generally speaking, when an ECC decoding failure or a RAID decoding failure is detected, an error handling mechanism running on the flash memory storage device would reclaim block(s) to which erroneous data belongs, and all data in the block(s) will be moved to other block(s) in the flash memory storage device to avoid potential data corruption. However, as storage density of the flash memory stage devices increases, the size of a single block has also increased significantly. The amount of data that needs to be moved due to the decoding failure would also increase significantly. In view of this, there is a need of providing a more efficient error handling mechanism to solve the above problems. SUMMARY OF THE INVENTION In view of this, it is one object of the present invention to provide an innovative error handling mechanism. In embodiments of the present invention, when moving data in response to errors, the error handling procedure will consider a range of data to be moved based on a protection range of RAID verification data. In other words, when an error occurs (such as a decoding failure in reading data or a programming failure in writing data), only the data associated with (e.g., protected by) the same RAID verification data will be moved. In this way, the amount of the data that needs to be moved is effectively reduced and the efficiency of error handling is also improved. In addition, as is known, the flash memory has a limited number of write/erase cycles (P/E cycles). Therefore, when the amount of data that needs to be moved during the error handling is reduced, the life span of the flash memory storage device can be extended while ensuring data security. According to one embodiment, an error handling method for use in a flash memory is provided. The error handling method comprises: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory. According to one embodiment, a memory controller for use in a flash memory is provided. The memory controller comprises: a storage unit and a processing unit. The storage unit is configured to store program code. The processing unit is configured to execute the program code to perform error handling procedure on the flash memory, comprising: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory. According to one embodiment, a data storage device is provided. The data storage device comprises a flash memory and a memory controller. The memory controller comprises: a storage unit and a processing unit. The storage unit is configured to store program code. The processing unit is configured to execute the program code to perform error handling procedure on the flash memory, comprising: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTIO